ECE Computer Engineering I. ECE Introduction. Z. Aliyazicioglu. Electrical and Computer Engineering Department Cal Poly Pomona

Transcription

1 ECE 34-2 Computer Engineering I ECE34-. Introduction Z. Aliyazicioglu Electrical and Computer Engineering Department Cal Poly Pomona Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34- Instructors Dr. Zekeriya Aliyazicioglu (Dr. Zeki) Office: zaliyazici@csupomona.edu Office Hours M 2: PM - 2: PM, W 2: PM - 2: PM, TH 3: PM - 4: PM Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-2

2 Course Description Analysis and design of Digital Systems using hardware (algorithmic state machines), and software (microcontrollers). Four (4) one-hour lecture/problem solving sessions. Prerequisites: ECE24/ 244, ECE22/27. Concurrent: ECE 34L. Note: Students are responsible for satisfying the required prerequisites. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-3 Course Objectives To teach students how to design algorithmic state machines To teach students how to use Verilog to describe and simulate digital systems To teach students the architecture, instruction set, and programming of the Motorola 68HC microcontroller To teach student important applications of a microcontroller. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-4

3 Text Book MC68HC: An Introduction, Software and Hardware Interfacing, Huang, 2 nd edition, ISBN Further Reading(s): Miller Gene H. Microcomputer Engineering, Prentice Hall, 2 nd Edition, 999. [2[ Motorola MC68HC Reference Manual, Motorola University Support Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-5 Grading Homework, uizzes, and Project effect the 25% of the final course grade Exam effects the 25% of the final course grade, Exam 2 effects the 25% of the final course grade, Final Exam effects the 25% of the final course grade Note : Students are responsible for all materials/announcements presented in class whether they are present or absent. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-6

4 Course Policies Students must have the pre/co requisites for ECE 34 as given above. No make-up tests will be given. Students are encouraged to discuss the course, including issues raised by the assignments. However, the solutions to assignments should be individual original work unless otherwise specified. You may ask a fellow student a question designed to improve your understanding, not one designed to get the assignment done. To do otherwise is to cheat yourself out of understanding, as well as to be dishonorable. Any case of cheating will result in an F grade for the course. Also, the case may be forwarded to the Department Chair for appropriate disciplinary action. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-7 Homework Homework must be turned in at the beginning of your class All work that you submit must represent your individual effort All assignments are expected to be prepared in a professional manner. No late homework assignments will be accepted Computer failure or lack of availability of a computer are not valid excuses for late assignments Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-8

5 uestions uestions before we begin? Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-9 Latch Latch : The memory element outputs immediately change in response to input change. Example : R-S latch. If a latch has only data input, like R and S, it is called unlocked latch. Level-sensitive latches have an additional enable input, sometimes called the clock or control input. Level-sensitive latches continuously sample their input while they are enabled. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-

6 Latch S 2 3 UA 74LS2 ' S' 2 3 UA 74LS2 2 3 U3A 74LS2 ' E' R 5 6 U2A 4 74LS2 R' 2 3 U2A 74LS2 2 3 U4A 74LS2 Unlocked R-S latch. Level-sensitive R-S latches S R Last Last S R Symbols for S-R latch undefined Function Table Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34- Flip-Flop Flip-Flops are different than latches Their outputs change only with respect to the clock. We can characterize flip-flops on the the basic of the clock transition that causes the output change. There are positive edge-triggered, negative edge-triggered, flip-flops A positive edge-triggered flip-flop samples its output on the low-to-high clock transition. The output change a propagation delay after rising clock transition A negative edge-triggered flip-flop samples its output on the high-to-low clock transition Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-2

7 D- Flip-Flop C D CK D CK D Clock Level-sensitive latch 74LS76 Clock Positive edge-triggered flip flop TTL 74LS74 Clock Negative edge-triggered flip flop Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-3 D- Flip-Flop D Clk Last Last Last O Last Timing behavior of s positive-edge-triggered D Flip-flop Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-4

8 The Trigger Flip-Flop (T Flip-Flop) T + FF T T R FF S R=T S= T T + + =T +T =T T= + Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-5 The Clocked Flip-Flop FF CK T Clock T T + Clock input has small circle indicates that the flip-flop changes state on the falling edge of the clock Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-6

9 R FF S The J-K Flip-Flop J K + CK K FF J + =K + J K J Construction from S-R FF + J K X X X X Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-7 The Clocked J-K Flip Flop FF K CK Clock J Clock J K Clock input has small circle indicates that the flip-flop changes state on the falling edge of the clock Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-8

10 The D Flip-Flop CK D D + Clock + =D D Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-9 Clocked FF with Clear and Preset Clear CLR PRE K CK J Clock J-K FF has Clear (CLR) and Preset (PRE) inputs. The small circle indicates that a logic is required to cleat or set the FF. Preset CLR= will reset the FF to = PRE= will set the FF =. This inputs override the clock and J-K inputs CLR and PRE should be normal J-K and clock operation. Clear CLR CK Clock D CLR= will reset the D Flip-Flop to = CLR inputs override the clock and D input When CLR =, D and clock input operate in normal. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-2

11 Design of a Binary Counter Let s design synchronous counter. This means the operation of the FF is synchronized by the common input pulse (P) Let s design a counter to count, 3, 5, 7, 2,6,,3,..and use T FF We can represent these integer numbers with 3 bits,,,,,,,,.. A B C A B C FF FF FF T A T B T C The State Graph Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-2 A B C A + B + C T A T B T C + T Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-22

12 Multiplexer (MUX), Decoders, Encoder, EPROM Cal Poly Pomona Electrical & Computer Engineering Dept. ECE Multiplexer A Multiplexer has a group of data inputs and group of control inputs The control inputs are used to select one of the data inputs and connect it to the output terminal Example: Data Input I I I 2 I 3 74x53 4-to- MUX F Data Input I I I 2 I 3 I 4 I 5 I 6 I 7 74x5 8-to- MUX F Control A B Input A B C Control Input A 4-to- Multiplexer A 8-to- Multiplexer Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-24

13 4-to- Multiplexer S S F I I I 2 I 3 F= S S I + S S I + S S I 2 + S S I 3 F Cal Poly Pomona Electrical & Computer Engineering Dept. ECE to- Multiplexer A' B' I A' B I A B' I F A B I 3 4-to- Multiplexer Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-26

14 2x Multiplexer Cal Poly Pomona Electrical & Computer Engineering Dept. ECE uadruple 2-to- Multipexer uadruple 2-to- Multipexer is used to select one of two- 4 bit data words If A=, the values of x,x,x 2,x 3 appears at the output If A=, the values of y,y,y 2,y 3 appears at the output z z z 2 z 3 A 2-to- 2-to- 2-to- 2-to- X y X y X 2 y 2 X 3 y 3 74x57 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-28

15 Using 4-to- MUX for any 3-variable function F(A,B,C)=A B +AC Two control inputs. Let s A and B F(A,B,C)=A B +AC(B +B) =A B +AB C+ABC C C I I I 2 I 3 4-to- MUX F A B Cal Poly Pomona Electrical & Computer Engineering Dept. ECE to- MUX can be used for 4-variable function AB CD I I 2 I 6 I 4 D D D D D I I I 2 I 3 I 4 I 5 I 6 I 7 8-to- MUX F I I 3 I 7 I 5 A B C Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-3

16 Dual 4x Mux.74LS53 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE INPUT MULTIPLEXER (74LS5) Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-32

17 Decoder Generates all of the minterms of the inputs variable One of the output lines will be for each combination of the input variables Example:3-to-8 decoder a b c Enable input n input 3-to-8 Line Decoder y =a b c y =a b c y 2 =a bc y 3 =a bc y 4 =ab c y 5 =ab c y 6 =abc y 7 =abc 2 n output a b c Y y y 2 y 3 y 4 y 5 y 6 y 7 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE LS39 A B G 2A 2B 2G 74LS39 y y Y 2 y 3 2y 2y 2y 2 2y 3 G A B X X y y y 2 y 3 2 input 4 output Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-34

18 74LS39 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE Design 4-to- decoder Decoder has inverted outputs a b c d Y y y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 m 9 a b c d 7442 m 7 m 5 m 3 m m 8 m 6 m 4 m 2 m Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-36

19 Design 4-to- decoder Cal Poly Pomona Electrical & Computer Engineering Dept. ECE Encoder Encoder performs a function that is the inverse of decoder An encoder has n outputs from 2 n inputs Enable input 2 n Data input enable Encoder n output LS47 2 n input 9 input 4 output Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-38

20 74LS47 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE Read-Only Memory Binary data is stored in the ROM. It can be read by the address given Each combination of input value, corresponding data appears on the output 3 Input Lines A B C ROM 8 Words X 4 Bits F F 2 F 3 F 4 4 Output Lines a b c F F 2 F 3 F 4 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-4

21 Read-Only Memory N input lines and m output lines contains an array of 2 n word, and each word is m bits long n Input Lines a a 2 a n. ROM 2 n Words X m Bits F F 2 M Output Lines F m a a 2.. a n Address Line F F 2. F m Data Array Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-4 Basic ROM Structure ROM n Input Lines. Decoder. Memory Array 2 n word x m bits m Output Lines Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-42

22 ROM Types Three Basic types of ROM Mask-programmable ROM At time of manufacture, the data array is permanently stored in a mask-programmable ROM. Field programmable ROM(PROM) Manufactured with all switching elements present in the memory array. Each intersection is made as a fusible link. To store the data, these fusible link selectively blown using voltage pulse. When the link blown, data is permanently stored in the array. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE ROM Types Erasable programmable ROM (EPROM) Instead of fusible links, EPROMs use a special chargestorage mechanism to enable or disable the switching links. The data stored in the array is generally permanent until it is erased using an ultraviolet light.after erased, e new set of data can be stored. EEPROM is similar to EPROM, except that electrical pulse use to erase it instead of ultraviolet. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-44

23 PLD (Programmable Logic Devices) Programmable Logic Device is a digital integrated circuit, which you can program it different logic function 2 to 4 functions of 4 to 6 variables with a single integrated circuit Designing system with PLD gives you option to change the program of PLD with out changing wiring. Cal Poly Pomona Electrical & Computer Engineering Dept. ECE Available PLD types: PLA (Programmable Logic Array) EPLD (Erasable PLD) PEEL (Programmable electrically erasable logic) GAL (General Logic Array) Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-46

24 PLA n Input Lines. AND Array. OR Array m Output Lines Cal Poly Pomona Electrical & Computer Engineering Dept. ECE PAL6R6 Cal Poly Pomona Electrical & Computer Engineering Dept. ECE 34-48