MLR Institute of Technology

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MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Phone Nos: 08418 204066 / 204088, Fax : 08418 204088

1 MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad Phone Nos: / , Fax : COURSE DESCRIPTION Course Title VLSI DESIGN Course Code Regulation R09 Course Structure Lectures Tutorials Practicals Credits Course Coordinator Team of Instructors Mr. P. Anudeep, Assistant Professor Mrs. T. Vijetha, Assistant Professor, Mr. J. Naga Raju, Assistant Professor I. COURSE OVERVIEW: VLSI design course gives the knowledge about the fabrication of NMOS, PMOS, CMOS and their application in the present electronics world. The present course gives knowledge about different processes used for fabrication of an IC. The electrical properties of MOS transistor and analysis of CMOS, BiCMOS inverters is carried out. This course gives detail study on design rules, stick diagrams, logic gates, types of delays, fan-in, fan-out which effects the action of a MOS. It also gives information on data path subsystem and array subsystems, and several PLD s like PLA, PAL, CPLD and FPGA s. We also came to the CMOS testing principles system level and chip level. II. PREREQUISITES: Level Credits Periods / Week Prerequisites UG 4 5 Electronic Devices and circuits, Switching Theory and Logic Design III. COURSE ASSESSMENT METHODS: Sessional Marks University Total End Exam Marks Marks There shall be 2 midterm examinations. Each midterm examination consists of subjective test and objective test. The subjective test is for 10 marks, with duration of 1 hour. Subjective test of each subject shall contain 4 questions; the student has to answer any 2 questions, each carrying 5 marks. The objective test is for 10 marks, with duration of 20 min. First midterm examination shall be conducted for the first four units of syllabus and second midterm examination shall be conducted for the remaining portion. Five marks are marked for assignments. There shall be two assignments in every theory course. First assignment marks will be allotted to 1 st mid for first four units and second assignment marks will be allotted to 2 nd mid for next four units. So each mid exam is conducted for 25 marks

2 IV. EVALUATION SCHEME: S. No Component Duration Marks 1 I Mid Examination 60 minutes 20 2 I Assignment II Mid Examination 60 minutes 20 4 II Assignment External Examination 180 minutes 75 V. COURSE OBJECTIVES: This course makes the students aware of the internal structure and manufacturing of a Transistor. And also the various levels involved in the chip designing and its manufacturing process. And design various gates, adders, Multipliers, Memories, using stick diagrams, layouts. VI. COURSE OUTCOMES: At the end of the course, the student will be able to: 1. Have the ability to synthesize static and dynamic logic cells based on knowledge of MOS device physics, modeling, and circuit topologies. 2. Be capable of designing and implementing combinational and sequential CMOS digital circuits and optimize them with respect to different constraints, such as area, delay, power, or reliability. 3. Be capable of implementing a complete design verification process using computerautomated tools for layout, extraction, simulation, and timing analysis. 4. Design and verify a prototype silicon integrated circuit suitable for fabrication using the μm CMOS process. 5. Have the ability to synthesize static and dynamic logic cells based on knowledge of MOS device physics, modeling, and circuit topologies VII. HOW PROGRAM OUTCOMES ARE ASSESSED: SNo. Program Outcomes 1 Describe ability to synthesize static and dynamic logic cells based on knowledge of MOS device physics, modeling, and circuit topologies. 2 Assess the capablity of designing and implementing combinational and sequential CMOS digital circuits and optimize them with respect to different constraints, such as area, delay, power, or reliability. 3 Assess the capablity of implementing a complete design verification process using computer- automated tools for layout, extraction, simulation, and timing analysis 4 Design and verify a prototype silicon integrated circuit suitable for fabrication using the μm CMOS process Level II IV IV III Proficiency assessed by Assignments Tutorial tutorial seminars

3 5 Decide ability to synthesize static and dynamic logic cells based on knowledge of MOS device physics, modeling, and circuit topologies V Assignments VIII. SYLLABUS: UNIT I INTRODUCTION Introduction to IC technology-mos, PMOS, NMOS, CMOS and BiCMOS Technologies: Oxidation, Lithography, Diffusion, Ion implantation, Metallization, Encapsulation, Probe testing, Integrated Resistors and Capacitors. UNIT II BASIC ELECTRICAL PROPERTIES Basic electrical properties of MOS and BiCMOS circuits: I ds -V ds relationships, MOS transistor threshold voltage, g m, g ds, figure of merit w o, pass transistor, NMOS inverter, Various pull-ups, CMOS inverter analysis and design, BiCMOS inverters. UNIT III VLSI CIRCUIT DESIGN PROCESSES VLSI design flow, MOS layers, Stick diagrams, Design Rules and Layout, 2 um CMOS design rules for wires, Contacts and Transistors, Layout diagrams for NMOS and CMOS inverters and gates, Scaling of MOS circuits UNIT IV GATE LEVEL DESIGN Logic gates and other complex gates, Switch logic, Alternate gate circuits, Time delays, Driving large capacitive loads, Wiring capacitances, Fan-in and fan-out, Choice of layers. UNIT V DATA PATH SUB SYSTEMS Sub system design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One detectors, Counters. UNIT VI ARRAY SUBSYSTEMS SRAM, DRAM, ROM, Serial Access Memories, Content Addressable Memory UNIT VII SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN PLAs, FPGAs, CPLDs, Standard cells, Programmable Array Logic, Design Approach, Parameters influencing low power design. UNIT VIII CMOS TESTING CMOS Testing, Need for testing, Test principles, Design strategies for test, Chip level test techniques, System-level test techniques, Layout design for improved testability. Text Books: 1. Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A. Pucknell, PHI, 2005 Edition. 2. VLSI DESIGN - K. Lal Kishore, V.S.V Prabhakar, I.K International, CMOS VLSI Design- Neil H.E Weste, David Harris, AyanBanerjee, Pearson Education, References:

4 4. CMOS logic circuit design- John P. Uyemura, Springer, Modern VLSI Design Wayne Wolf, Pearson Education, 3 rd Edition, Introduction to VLSI-Mead and convey, BS publications, Application Specific Integrated Circuits-smith IX. COURSE PLAN: At the end of the course, the students are able to achieve the following course learning outcomes (CLO): Lecture UNI Course learning outcomes Topics to be covered Book No. T 1 I Discuss and memorize the IC Introduction to IC T1 generations, importance of VLSI Technology MOS, PMOS To know fabrication of PMOS 2-3 Describe fabrication of NMOS NMOS technology T1 4-5 Describe fabrication of CMOS CMOS technologies T1 6-7 Describe fabrication of Bi CMOS Bi CMOS technologies T1 8 Outline ion implantation, diffusion Diffusion, Ion implantation, T1,oxidation, lithography Metallization 9 Describe Encapsulation, Probe T1 Encapsulation, Probe testing, testing, Integrated Resistors Integrated Resistors, capacitors II Identifythe threshold voltage concept Basic Electrical Properties T1 and Basic Electrical Properties of MOS and Bi-CMOS Circuits Depending on V GS I ds -V ds relations I ds -V ds relationships, MOS are derived transistor threshold Voltage T1 14 Illustrateabout the pass transistor,w o gm, gds, figure of merit w o, Pass transistor T1 15 Illustratevarious pull up Various pull-ups, Identifywhy we are preferring CMOS CMOS Inverter analysis and T1 technology design, Bi-CMOS Inverters 18 III Describe the design flow Design Flow, MOS Layers T Discussstickdiagram representation Stick Diagrams, Design T1 and illustrate the concept of stick diagram representation. Rules and Layout Examine the concept of layout and 2 um CMOS Design rules T1 study required rules. for wires, Contacts and Transistors Discuss the construction of study Layout Diagrams for NMOS T1 layout rules for different processes and and CMOS Inverters and to learn how to draw layouts. Gates 25 Discuss and memorize the scaling and Scaling of MOS circuits T1 effects of scaling. Identify the limitations of scaling IV Analyse gate design by CMOS and Logic Gates and Other T1 nmos logic. complex gates, Switch logic Illustrate gate design and distinguish Alternate gate circuits, Time T1 between CMOS and nmos logic. Delays Discussdriving large Capacitive Driving large Capacitive T1 Loads, Wiring Capacitances Loads, Wiring Capacitances 33 Describeabout Fan-in and fan-out, Fan-in and fan-out, Choice T1 Choice of layers of layers V DesignShifters, Adders Subsystem Design, Shifters, T3

5 Adders designalus, Multipliers, Parity ALUs, Multipliers, Parity T3 generators generators design Comparators, Zero/One Comparators, Zero/One T3 Detectors, Counters Detectors, Counters VI design memories SRAM, DRAM, SRAM, DRAM, ROM T3 ROM Design of serial access memories, Serial access memories, T3 content addressable memory content addressable memory VII Design of PLAs, FPGAs, CPLDs PLAs, FPGAs, CPLDs R4 53 Advantages of Programmable Array Standard Cells, R4 Logic Programmable Array Logic VIII Illustrate parameters influencing low Design Approach, R4 power design parameters influencing low power design Demonstrate the need for testing. CMOS Testing, Need for T3 testing, Test Principles ToIllustrate the different test Design Strategies for test, T3 techniques To acquaint with the chip Chip level Test Techniques level testing techniques To Discuss with the system level System-level Test T3 testing techniques. Techniques, Layout Design for improved Testability X. MAPPING COURSE OBJECTIVES LEADING TO THE ACHIEVEMENT OF PROGRAM OUTCOMES: Course Objectives Program Outcomes a b c d e f g h i j k l m

6 XI.MAPPING COURSE OUTCOMES LEADING TO ACHIEVEMENT OF PROGRAM OUTCOMES: Course Outcomes Program Outcomes a b c d e f g h i j k l m Prepared by: Mr. P. Anudeep, Assistant Professor HOD, COMPUTER SCIENCE AND ENGINEERING

EE 579: Digital System Testing. EECS 579 Course Goals

EE 579: Digital System Testing Lecture 1: Course Introduction and Overview John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 1 EECS 579 Course Goals To learn about The role of testing