ECE Computer Engineering I. Z. Aliyazicioglu. Electrical and Computer Engineering Department Cal Poly Pomona

Transcription

1 EE 34-4 omputer Engineering I EE34-2. equential Network Z. Aliyazicioglu Electrical and omputer Engineering epartment al Poly Pomona al Poly Pomona Electrical & omputer Engineering ept. EE 34-2 egister egisters are formed from a collection of flip-flops, like counters. ata storage is the main function of a register clock Load data x x data clock data data Parallel Input/Output erial Input/Output clock Load data x data clock Load data x data Parallel Input/erial Output erial Input/ Parallel Output al Poly Pomona Electrical & omputer Engineering ept. EE

2 Parallel Input/Output egister lock lock clear Output ata 8 Bit egister using 2x4 bit register clear 4 Bit egister al Poly Pomona Electrical & omputer Engineering ept. EE ight-shift erial Input Output egister lock t 6 t t 2 t 3 t 4 t 5 In al Poly Pomona Electrical & omputer Engineering ept. EE

3 ounter Asynchronous Up-ounter with Flip Flip lock 2 lock al Poly Pomona Electrical & omputer Engineering ept. EE ounter Asynchronous own-ounter with Flip Flip lock 2 lock al Poly Pomona Electrical & omputer Engineering ept. EE

4 ounter ynchronous 4-bit Up counter with Flip-Flop 2 3 lock lock changes 2 changes = = 2 = 3 = 2 n = n- 7 al Poly Pomona Electrical & omputer Engineering ept. EE locked equential Network We will consider sequential networks which have clock pulse input and additional inputs. o that sequence of output flip-flop states will depend on the input sequence. wo types of clocked sequential network will be considered.. Moore machine he output depends only on the present state of the flip-flop which is referred as a Moore machine. he outputs change synchronously with the state transition and the clock edge. Inputs ombinational Network E tate egister ombinational Network Outputs E=f(Input, t ) Output=f( t ) lock Feedback t+ =f(e, t ) al Poly Pomona Electrical & omputer Engineering ept. EE

5 Mealy machine 2. Mealy machine he output depends on the present state and the present value of the inputs which is referred as Mealy machine. he output can change immediately after a change at the inputs, independent of the clock. Mealy machine has asynchronous output. Inputs ombinational Network Feedback G E tate egister lock om. Network E=f(Input, t ) Outputs t+ =f(e, t ) Output=f(G, t ) al Poly Pomona Electrical & omputer Engineering ept. EE tate iagram he symbolic notation for a one input, one output Mealy sequential circuit state diagram X /Y X/Y X/Y 2 X : input Variable Y : Output variable X /Y and are symbols representing different states X/Y indicates input/output If input variable X=, then the machine remains in state and Output is If input variable X=, then transition to state 2 and Output is he output is is a function of both the present state and the input al Poly Pomona Electrical & omputer Engineering ept. EE 34-2

6 In Moore machine, the output is dependent on only the present state. We represent the output inside of the state circle. Here is an example of state graph for Moore circuit notations of a J-K flip-flop,,, 2, Output variables written under state Variable names If is present state, then If JK= and machine remains state and output is If JK= and transition to state 2 and the output changes to If 2 is present state, then If JK= and machine remains state 2 and output is If JK= and transition to state and the output changes to al Poly Pomona Electrical & omputer Engineering ept. EE 34-2 esign a clocked Mealy sequential network Network will examine a string of s and s applied to the X input and generate an output Z= only when a prescribed input sequence occurs. he input X can only change between clock pulses. We will design a network so that any input sequence ending in will produce an output Z= coincident with the last. he network does not reset when a output occurs. A ypical input and corresponding output sequences X= Z= al Poly Pomona Electrical & omputer Engineering ept. EE

7 Let s start with two state,, Later we will assign FF states to corresponding to the network states. Initially we start the network in a reset state. If the input X= is received, the network can stay in. If X= is received, it will go to next state he label on the graph shows X/Z which X is input and Z is corresponding output. / / / / / / / 2 / Mealy tate Graph for equence Net. al Poly Pomona Electrical & omputer Engineering ept. EE onverting the state graph to a state table Present tate 2 Next tate X= X= 2 Present Output X= X= We have three states, so we need two FF since one FF has two states. Let FF states A=, B= correspond to network state, A=,B= correspond to networks state. A=,B= correspond to networks state 2. Present tate AB Next tate A + B + X= X= Z X= X= al Poly Pomona Electrical & omputer Engineering ept. EE

8 X AB x x A + =X B X AB x x X AB x x B + =X Z=XA al Poly Pomona Electrical & omputer Engineering ept. EE Let s use F-F. A =A + =X B and B =B + =X K A A K B B Z X al Poly Pomona Electrical & omputer Engineering ept. EE

9 esign a clocked Moore sequential network Moore machine is similar to Mealy machine except that the output is written with the state instead of with the transition between states. We will do the same problem with moore machine. In Moore machine the output will be associated with states,, and 2 2 al Poly Pomona Electrical & omputer Engineering ept. EE onverting the state graph to a state table Present tate 2 3 Next tate X= X= Present Output Z We have four states, so we need two FF since one FF has two states. Let FF states AB= for state, AB= for AB= for 2,,. AB= for state 3, Present tate AB Next tate A + B + X= X= al Poly Pomona Electrical & omputer Engineering ept. EE Z

10 X AB A + =A BX +AB X +ABX X AB B + =A B+AB +A X Z=AB al Poly Pomona Electrical & omputer Engineering ept. EE Z K A A K B B lock X al Poly Pomona Electrical & omputer Engineering ept. EE

11 Homework- uestion- onstruct a Mealy state diagram that will detect a serial input sequence of. When the input pattern has been detected, cause an output z to be as. ypical input and corresponding output sequence X= Z= al Poly Pomona Electrical & omputer Engineering ept. EE equential ircuit Analysis al Poly Pomona Electrical & omputer Engineering ept. EE

12 etermine system variables Input = x Output = z tate variables = F 2 and F Assign Variables names. hey are assigned already etermine F-F type. hey are type he characteristic equation is + = Write the excitation equation by inspection ' ' ' 2 = FFx 2 = x + F2F Write the next state equations F FFx + ' 2 = 2 F + = x + F F ' ' 2 al Poly Pomona Electrical & omputer Engineering ept. EE onstruct the excitation table X F 2 F F 2 F X Excitation K-maps for 2 and F 2 F X F 2 F X K-Maps for etermine next state term F + 2 and F + al Poly Pomona Electrical & omputer Engineering ept. EE

13 Write the output variable equation Z=F 2 x X F 2 F onstruct the transition table. rate this from Excitation K-maps or next state k-maps and output k-maps z F + 2 = 2 = + = f F2 F x = = f F2 F x = F f( F, F, x) (3) (,, ) (,2,3,4,6) (,, ) (5,7) al Poly Pomona Electrical & omputer Engineering ept. EE ransition and excitation table Present tate F F + F + 2 F + 2 F z 2 F + z Next tate Present able Next state x/z A B z z B A B B A B A tate table al Poly Pomona Electrical & omputer Engineering ept. EE

14 tate iagram for analysis example x/z x /z A x /z x /z B x/z x/z x /z x/z al Poly Pomona Electrical & omputer Engineering ept. EE iming iagram al Poly Pomona Electrical & omputer Engineering ept. EE

15 X Homework- uestion2 B A A Z A B B lock Given the logic diagram in the following figure. Write the excitation and output equations 2. Write the next state equations 3. onstruct a transition table 4. raw the state graph 5. omplete the following time diagram al Poly Pomona Electrical & omputer Engineering ept. EE x B A z al Poly Pomona Electrical & omputer Engineering ept. EE