EOS/ESD SYMPOSIUM AND EXHIBITS. company

Transcription

1 September 23-28, 2018 Peppermill Resort Spa Casino, Reno, NV, USA 40TH ANNUAL EOS/ESD SYMPOSIUM AND EXHIBITS Solve your ESD Challenges - Learn from Industry Experts Network with all of the top ESD Professionals in every major company We have had this event for 40 years! Celebrate with us and see why! Co-sponsored by: IEEE Learn best practices and the newest advances in technology f ESD control, protection, and design Attend the EOS/ESD Symposium featuring information and education: Devices, Boards, and Systems Latest research on EOS and ESD in the rapidly changing world of electronics RETURN of the MANUFACTURING TRACK: Manufacturing focused sessions with hands-on courses, discussion groups, and short tutorials 16 New sessions IoT Workshop Setting the Global Standards for Static Control! 1998 EOS/ESD Association, Inc Turin Rd., Bldg. 3 Rome, NY , USA PH info@esda.org July 18, :29 PM 2008

2 Welcome Dear colleagues, friends, and fellow EOS/ESD enthusiasts, On behalf of EOS/ESD Association, Inc. and the 2018 Symposium Steering Committee, it is my honor to welcome you to the 40th Annual EOS/ESD Symposium and Exhibits at the Peppermill Resort and Casino, in Reno, Nevada. To celebrate our 40th Symposium we have prepared an exciting program packed with tutorials, exhibits, workshops, discussion groups, technical sessions, invited talks, hands-on sessions, and a few surprises. Continuing in the tradition started last year we structure the Symposium in separate design and manufacturing tracks. Finally, as a special treat for the 40th Symposium, we are hosting a first ever Workshop on Robustness of IoT Devices. Here is a short summary of what to expect. 39 Tutorials: A dedicated team of experts, in all areas of EOS and ESD, have been working diligently all year to prepare the tutorial program. Tutorials are offered on Sunday, Monday, and Thursday. This year, several new tutorials are introduced, including Practical Applications of Ionization, Latch-up Basics and Testing, What information needs to be exchanged for potential EOS problems?, Design Engineer - Weak Link or Warrior in the ESD Battle?, Introduction to RF ESD Design, and Emerging Topics - Technology and ESD challenges towards 7 nm. Many previously offered tutorials have been refreshed with updated material. Over 40 Exhibitors: Our industry exhibits display a wide variety of ESD solutions from established products to leading-edge innovations. Representatives from many different companies welcome you in the exhibit hall to demonstrate their products and services, starting with the welcome reception on Monday evening and continuing until the exhibits close on Wednesday afternoon. The exhibits offer a unique opportunity to meet professionals with hands-on experience on static control methods, evaluation techniques, ESD testing hardware, and many other ESD solutions. Technical Program Keynote: Presented as the highlight of the Awards Breakfast, this year s Keynote is Electrified Automobility Protecting Driver and Electronics by Dr. Hans Stork, of ON Semiconductor. Design Track - 36 Peer-reviewed + 4 Invited Technical Papers: These will be presented Tuesday through Thursday in 12 sessions covering hot topics in the areas of advanced CMOS, RF/HV/MEMS, system-level ESD/modeling/soft failures, ESD transient analysis, ESD case studies, EOS/ESD EDA tools, numerical modeling, and ESD testing. The papers are presented by industry experts driving leading edge research and development. Manufacturing Track - 10 Peer-reviewed papers in two technical sessions. Furthermore, the Manufacturing Track includes 2 Sessions with 3 short tutorials each, 2 hands-on sessions, 2 invited groups, and 3 discussion groups. 2 Year-in-Review Presentations: This year s program again features two year-in-review presentations. Reinhold Gaertner of Infineon Technologies AG will present recent developments on EOS and Harald Gossner of Intel will give an update on System-Level ESD. 8 Workshops: Symposium workshops, which take place on Tuesday and Wednesday afternoons, offer an interactive forum for sharing experiences, exchanging knowledge, and defining possible solutions. All workshops are centered on relevant and timely technical topics. Each workshop allows participants the opportunity to learn different perspectives from other colleagues in the field and allow the discussion of sometimes controversial topics in an informal environment. The popular world café style workshop will return this year again, with the topic Can Everyone Agree on What AMR Means? Robustness of IoT Devices Workshop: We are excited to host this new one-and-a-half-day workshop to the Symposium program. Eleven invited speakers with unique industry-wide IoT expertise will cover challenges of meeting reliability and robustness requirements. Join us to learn and network with industry experts. 40th Annual Symposium Celebration: We have a special celebration planned on Tuesday, September 25th, and all Symposium attendees and exhibitors are invited! Plan to join us as we reminisce and celebrate 40 great years of the EOS/ESD Symposium. Don t miss it. Don t forget the General Chair s Reception on Wednesday September 26th from 7:00 PM to 9:00 PM. Everyone is invited! The EOS/ESD Symposium is the premier international event for professionals in industry and academia to network while immersed in the latest technical findings and innovative designs. Have fun! Sincerely, Jim Miller, NXP 2018 EOS/ESD Symposium General Chair 2

3 Table of Contents Registration, Fees, Hours...4 General Information...4 Welcome Reception...4 Annual Meeting and Awards Breakfast...4 Professional and Technical Women s Reception... 4 General Chair s Reception...4 Invited Breakfast University Students/Professors...4 First Time Attendee Social Hour...4 Schedule Keynote...8 Professional Certification...9 Tutorials Technical Sessions Workshops Exhibits...41 ESDA Officers, Board of Directors, and HQ Staff Steering Committee...42 Technical Program Committee...42 Hotel Reservations & Information...43 Registration Form Upcoming Announcemnets th Symposium Celebration Event All Symposium attendess are invited to the 40th annual celebration event! The celebration starts at 6:30pm with a social reception honoring Ed Weggeland. Following the reception will be dinner and entertainment. Enjoy the fun and network with other symposium attendees. Register Online! 3

4 On-Site Registration Hours Registration will be open at the following times: Sunday, September 23 7:30 a.m. - 5:00 p.m. Monday, September 24 7:30 a.m. - 5:00 p.m. Tuesday, September 25 7:30 a.m. - 5:00 p.m. Wednesday, September 26 7:30 a.m. - 5:00 p.m. Thursday, September 27 7:30 a.m. - 5:00 p.m. Save by registering in advance! This will facilitate your registration upon your arrival at the Symposium. Early registration and member discounts* are valid only if received no later than July 24, Symposium $800 (Includes technical sessions, workshops, and exhibits) Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $600/Non-Members $700 Tutorials $710 (Sunday, Monday, OR Thursday (Full Day)) Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $510/Non-Members $610 Bundled Fees $2,465 (Symposium plus Sunday, Monday, and Thursday full tutorial days) Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $1,765/Non-Members $2,165 ESD Program Development and Assessment (ANSI/ESD S20.20) $1,710 (Attendance limited to first 30 registrants) This two-day tutorial is not included in the bundled fee. Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $1,510/Non-Members $1,610 *Membership discounts apply to those who participate as members all year long and are current at the opening of symposium registration. Memberships processed after this date will not apply. You will receive a complimentary 2019 membership with your Symposium registration which will allow you to enjoy the full benefits of membership in Register 5 or more people from one company at the same time and save $100 per person. Please contact EOS/ESD Association, Inc. prior to registering. Refunds cannot be issued. General Information continued Hospitality Suites To maintain the objectives of the Symposium, EOS/ESD Association, Inc. encourages all exhibitors and guest organizations to schedule their hospitality and other social events at times that do not conflict with the Symposium presentations and educational activities. Age Limits No one under 18 years of age will be admitted to the exhibit hall. Unauthorized Solicitation Solicitation of business on the premises during the EOS/ESD Symposium by manufacturers or others who are not participating as exhibitors is prohibited. Recording Video and/or audio recording of Symposium events is prohibited without the prior written authorization of EOS/ESD Association, Inc. Welcome Reception A welcome reception for all attendees will be held on Monday, September 24, at 6:00 p.m. in the exhibit hall. Network with your colleagues, share your ESD work experiences with others, view the exhibits, or simply pass the time meeting new people and making new friends. The 2018 Steering Committee will greet you and answer any questions regarding the Symposium. Annual Meeting and Awards Breakfast The annual meeting and awards breakfast for all registered attendees and exhibitors will be held Tuesday, September 25, at 7:30 a.m. Following breakfast, General Chair, Jim Miller, will officially open the Symposium. Vice General Chair, Guido Notermans, will present the 2017 EOS/ESD Symposium paper awards. Technical Program Chair, Lorenzo Cerati, will cover highlights of the 2018 technical program. Association President, Ginger Hansel, will present the Association s annual report. Awards Chair, Charvaka Duvvury, will present the 2018 Association awards. Student Fees EOS/ESD Association, Inc., offers a fifty percent discount and waived fees to all Symposium tutorials for full-time students (first author only). Proof of enrollment required. Student fees apply only to symposium and tutorial registration and do not apply to bundled fees or ANSI/ESD S20.20 two day tutorial. General Information Symposium Proceedings Each paid registrant receives one electronic copy of the proceedings. Tutorial Notes Customized, full color tutorial notes will be provided to each tutorial registrant. Professional and Technical Women s Reception The Professional and Technical Women s Reception provides a friendly environment where women in the field of ESD can network and share work experiences. This year s reception will be held on Monday, September 24, from 5:00 to 6:00 p.m. NEW University Students/Professors Invited to Wednesday Breakfast with ESDA Management Wednesday, Septmber 26, 7:00am-8:00am NEW First Time Attendee Social Hour Thursday, September 27 12:30-1:30 General Chair s Reception Jim Miller invites attendees to the general chair s reception on Wednesday, September 26, from 7:00 pm to 9:00pm. Poster presentations of technical papers from all sessions will be on display. Don t miss this opportunity to network and share informal conversation with authors, industry professionals, and peers. Register Online! 4

5 SUNDAY, SEPTEMBER 23, 2018 Registration 7:30 a.m. - 5:00 p.m. S :00 a.m. - 5:00 p.m. FC340: ESD Program Development and Assessment (ANSI/ESD S20.20) (PrM) (Day 1) Tutorials 8:00 a.m. - 12:00 p.m. DD110: ESD Basics to Advanced Protection Design (DD) 8:00 a.m. - 5:00 p.m. FC100: ESD Basics for the Program Manager (PrM) 8:30 a.m. - 12:00 p.m. DD200: Charged Device Model Phenomena, Design, and Modeling (DD) 8:30 a.m. - 12:00 p.m. FC165: Novel Methods for Fixing ESD Issues in the Factory for both Electronics & Explosive Products 8:30 a.m. - 12:00 p.m. DD/FC130: System Level ESD/EMI: Testing to IEC & Other Standards (PrM), (DD) 8:30 a.m. - 12:00 a.m. FC200: Packaging Principles for the Program Manager (PrM) 1:00 a.m. - 4:30 p.m. DD311: Impact of Technology Scaling on Components High Current Phenomena and Implications for Robust ESD Design (DD) 1:00 p.m. - 4:30 p.m. DD201: ESD Protection and I/O Design 1:00 p.m. - 4:30 p.m. DD204: ESD Design in HV Technologies 1:00 p.m. - 4:30 p.m. FC365: Practical Applications of Ionization 1:00 p.m. - 4:30 p.m. FC370: Basics of EMI and EOS in Manufacturing Environment and its Mitigation MONDAY, SEPTEMBER 24, 2018 Registration 7:30 a.m. - 5:00 p.m. S :00 a.m. - 5:00 p.m. FC340: ESD Program Development and Assessment (ANSI/ESD S20.20) (PrM) (Day 2) Tutorials 8:30 a.m. - 4:30 p.m. FC101: How To s of In-Plant ESD Auditing and Evaluation Measurements (PrM) 8:30 a.m. - 12:00 p.m. DD100: ESD Circuits 8:30 a.m. - 12:00 p.m. DD231: ESD System Level: Physics, Testing, Debugging of Soft and Hard Failures 8:30 a.m. - 12:00 p.m. FC120: Air Ionization Issues and Answers for the Program Manager (PrM) 8:30 a.m. - 12:00 p.m. DD/FC250: What Information Needs to be Exchanged for Potential EOS Problem 8:30 a.m. - 10:00 a.m. DD115: Latch-Up Basics and Testing 10:30 a.m. - 12:00 p.m. DD117: TCAD Fundamentals 1:00 a.m. - 4:30 p.m. DD300: Circuit-Level Modeling and Simulation of On-Chip Protection (DD) REVISED 1:00 p.m. - 4:30 p.m. DD340: Integrated ESD Device and Board Level Design 1:00 p.m. - 4:30 p.m. FC215: Device Technology and Failure Analysis Overview (PrM) 1:00 p.m. - 2:30 p.m. DD/FC330: Control of Charged Board Event (CBE) 1:00 p.m. - 2:30 p.m. DD317: ESD Challenges in Advanced FinFET and GAA NW CMOS Technologies 3:00 p.m. - 4:30 p.m. FC201: ESD - A Surprisingly Frequent Root Cause of Device Failure Emerging topic 3:00 p.m. - 4:30 p.m. Technology and ESD Challenges Towards 7 nm Reception 5:00 p.m. - 6:00 p.m. Professional and Technical Women s Reception Welcome Reception 6:00 p.m. - 9:00 p.m. Exhibits Open TUESDAY, SEPTEMBER 25, 2018 Registration 7:30 a.m. - 5:00 p.m. Awards Breakfast 7:30 a.m. - 9:45 a.m. Annual Meeting and Awards Breakfast Keynote 9:00 a.m. - 9:45 a.m. Electrified Automobility - Protecting Driver and Electronics Dr. Hans Stork Exhibits Open 9:30 a.m. - 5:30 p.m. Technical Sessions 10:00 a.m.-10:10 a.m. Exhibitor Showcase in Session 1A and 1B 10:10 a.m.-12:15 p.m. 1A: Advanced CMOS 10:10 a.m.-12:15 p.m. 1B: Manufacturing I 1:25 p.m. - 2:45 p.m. Hands On Session I Manufacturing Track Process Assessment Measurements 1:25 p.m. - 1:35 p.m. Exhibitor Showcase in Sessions 2A and 2B 1:35 p.m. - 2:50 p.m. 2A: System Level ESD l 1:35 p.m. - 2:50 p.m. 2B: RF / High Voltage & MEMS I 3:20 p.m. - 3:30 p.m. Exhibitor Showcase in Sessions 3A and 3B 3:30 p.m. - 4:45 p.m. 3A: System Level Modelling 3:30 p.m. - 4:45 p.m. 3B: RF & High Voltage & MEMS ll 3:25 p.m. - 4:45 p.m. Manufacturing Track - Invited Speaker Session 3:25 p.m. - 4:05 p.m. I: ESD in Health Care 4:05 p.m. - 4:45 p.m. II: How to Achieve Return on Investment in ESD Control Study Session 5:00 p.m. - 6:00 p.m. Calculations and ESD Scenarios Review for ESD Program Manager Exam Preparation (STUDY SESSION) Workshops A 5:05 p.m. - 6:20 p.m. A.1 Industry Council s Next Thresholds Targets - Do We Need Lower Targets, and Can We Achieve Them? A.2 EDA Solutions for ESD System Level A.3 Latch-up Testing - JESD78F and Beyond A.4 Process Assessment of Automated Handlers 40th Celebration Event 6:30 p.m. - 9:30 p.m. Social reception, dinner, entertainments, etc. Open to all atendees. 5

6 WEDNESDAY, SEPTEMBER 26, 2018 Invited Breakfast 7:00 a.m. - 8:00 a.m. University Students/Professors Invited to Breakfast with ESDA Management Registration 7:30 a.m. - 5:00 p.m. Exhibits Open 8:30 a.m. - 1:30 p.m. Technical Sessions 8:00 a.m. - 8:40 a.m. Year in Review: EOS the Real Challenge or End Of Story (of Communication)? 8:50 a.m. - 9:00 a.m. Exhibitor Showcase in Session 4A & 4B 9:00 a.m. - 10:40 a.m. 4A: System Level Soft Failures 9:00 a.m. - 11:05 a.m. 4B: Manufacturing II 1:00 p.m. - 1:30 p.m. Welcome to the IoT Workshop 1:30 p.m. - 5:00 p.m. IoT Workshop Session A 1:30 p.m. - 2:15 p.m. A1: IoT Technologies for the Developing Countries: Opportunities & Challenges 2:15 p.m. - 3:00 p.m. A2: Cognitive Control of Building HVAC Systems -- Challenges and Lessons Learned 3:15 p.m. - 4:00 p.m. A3: IoT Challenges Through Three Examples 4:00 p.m. - 4:45 p.m. A4: If You Lower Your Shields - System Level Implications of Losing Layers of Surge Protection in Safety-Critical IoT 1:15 p.m. - 1:25 p.m. Showcase: IC Data Advanced Topics Committee 1:25 p.m. - 3:25 p.m. Hands On Session II Manufacturing Track 1:25 p.m. - 1:35 p.m. II.A ESD Body Walking Voltage Measurement Demonstration 1:35 p.m. - 1:45 p.m. II.B Hand Tools and Soldering Irons - Qualification and Compliance Verification 1:45 p.m. - 2:25 p.m. ll.a, ll.b Demo Session 2:25 p.m. - 2:35 p.m. II.C Ionizer Compliance Verification Process 2:35 p.m. - 2:45 p.m. II.D Package Characterization 2:45 p.m. - 3:25 p.m. ll.c, ll.d Demo Session 1:35 p.m. - 3:15 p.m. 5A: System Level ESD ll 1:35 p.m. - 3:15 p.m. 5B: EOS/ESD EDA Tools 1:25 p.m. - 3:15 p.m. 6A: Testing 3:45 p.m. - 5:25 p.m. 7A: ESD Transient Analysis 3:40 p.m. - 5:25 p.m. Tutorial Session I: Manufacturing Track I.A Meet ESD TR I.B Changes in ESD/EOS Manufacturing and Control Standards I.C Troubleshooting of ESD Issue in Manufacturing Floor Workshops B 5:45 p.m. - 7:00 p.m. B.1 Can Everyone Agree on what AMR Means? B.2 System Level Testing (CDE, CBE, HMM, etc.) - What Does Industry Really Need? B.3 Qualification of Packaging Material - Use of Packages Outside of an EPA B.4 IoT Workshop - What is Different in Regards to Robustness Requirements in a connected World of IoT Devices Reception 7:00 p.m. - 9:00 p.m. General Chair s Reception Open to all Symposium Attendees! THURSDAY, SEPTEMBER 27, 2018 Registration 7:30 a.m. - 5:00 p.m. Technical Sessions 8:00 a.m. - 8:40 a.m. Year in Review: System Level ESD Design 8:50 a.m. - 10:20 a.m. Discussion Group Session Manufacturing Track DG.A EOS/ESD Control Program Concerns and Solutions DG.B ESD Best Practices when Handling Explosives and Energetic Components DG.C System Level ESD Simulations 8:50 a.m. - 10:30 a.m. 8A: Numerical Modeling 9:00 a.m. - 12:30 p.m. IoT Workshop Session B 9:00 a.m. - 9:45 a.m. B1: Building a Robust and Secured IoT Edge Device with Advanced Semiconductor Technology 9:45 a.m. - 10:30 a.m. B2: Improving the System Integration of Future IoT Devices Using Simulations: Design Approaches and Challenges 10:45 a.m. - 11:30 a.m. B3: Heterogeneous Integrated Edge Device Design: Pave the Road to Robust IoT System 11:30 a.m. - 12:15 p.m. B4: Convergence of Electromagnetic Engineering in Systems 10:50 a.m. - 12:05 a.m. 9A: ESD Test Cases 10:40 a.m. - 12:25 p.m. Tutorial Session II Manufacturing Track II.A Suspect Counterfeit ESD Packaging and Materials have Infiltrated the Comercial & DOD Supply Chain II.B Limitiations of Test Equipment and Understanding Measurement Results II.C Common ESD Problems in Manufacturing 1:30 p.m. - 3:45 p.m. IoT Workshop Session C&D C1: Is 1kV Also Enough for IoT ESD Protection - Do Current Test Methods and Models Apply? D1: How Amazon Builds Robust Consumer and Smart Home Products? D2: ESD Robustness of IoT Devices: Are We Going to Face New Challenges? 4:00 p.m. - 4:45 p. m. IoT Workshop Panel Discussion 4:45 p.m. - 5:00 p.m. IoT Workshop Closing Social Hour 12:30 p.m. - 1:30 p.m. First Time Attendee Social Hour 6

7 THURSDAY, SEPTEMBER 27, 2018 (CONTINUED) Tutorials 8:30 a.m. - 4:30 p.m. FC170: ANSI/ESD S20.20 ESD Program Assessment for Internal Auditors and Supplier Quality Engineers 8:30 a.m. - 12:00 p.m. DD260: Design for EOS Reliability 8:30 a.m. - 12:00 p.m. DD150: Introduction to RF ESD Design 8:30 a.m. - 12:00 p.m. FC110: Cleanroom Considerations for the Program Manager (PrM) 8:30 a.m. - 12:00 p.m. FC361: ESD Controls for CDM and Ultra-Sensitive Devices and Circuit Boards 8:30 a.m. - 10:00 a.m. DD/FC165: Design Engineer - Weak Link or Warrior in the ESD Battle 10:30 a.m. - 12:00 p.m. DD213: ESD, EOS, and Latch-up Failure Analysis for Designers 1:00 p.m. - 4:30 p.m. DD220: Transmission Line Pulse (TLP) Basics and Applications (DD) 1:00 p.m. - 4:30 p.m. FC262: Electrical Fields and Particles - Practical Considerations for the Factory 1:00 p.m. - 4:30 p.m. FC150: Hands-on ESD Measurements & Instruments - Uses and Pitfalls 1:00 p.m. - 4:30 p.m. FC360: Electrical Overstress (EOS) in Manufacturing and Test 1:00 p.m. - 2:30 p.m. DD381: Electronic Design Automation (EDA) Solutions for ESD 3:00 p.m. - 4:30 p.m. DD382: Electronic Design Automation (EDA) Solutions for Latch-up FRIDAY, SEPTEMBER 28, :00 a.m. - 5:00 p.m. Device Design Certification Exam 8:00 a.m. - 5:00 p.m. Program Manager Certification Exam 7

8 KEYNOTE Tuesday, September 25 9:00 a.m. - 9:45 a.m. Electrified Automobility Protecting Driver and Electronics With the expected rapid increase of automotive electrification, all but few functions of the automobile will be electronic. Power devices and image sensors are becoming essential components to realize the future of automobility. They will need to survive the extreme use / stress conditions (temperature, humidity, vibration) and meet the consumer expectations (zero failures and affordable cost). This talk will review recent progress in high power integrated circuit processes for drivetrain and other mechanical functions, discrete power devices for battery management and electromotor control, and image sensors for ADAS support, highlighting unique restrictions to manage stress conditions. The challenge of simultaneously meeting a wide range of power density, temperature, cost, and reliability requirements is feasible thanks to ongoing progress in understanding, modeling, and innovation. Dr. Hans Stork is Senior Vice President and Chief Technology Officer (CTO) at ON Semiconductor. He oversees the development of wafer process technologies, modeling and design kits, and design libraries, as well as packaging technologies and assembly support. Prior to joining ON Semiconductor, Dr. Stork was group vice president and CTO of the Silicon Systems Group at Applied Materials. From 2001 to 2007 he was senior vice president and the CTO of Texas Instruments. Before that, Dr. Stork held various R&D and management positions at Hewlett Packard Laboratories and at IBM s T.J. Watson Research Center. Dr. Stork serves on the supervisory board of ASML, is a member of the scientific advisory board at IMEC, and has previously served on the boards of Sematech and the SRC. He is also a longstanding member of the SIA Technology Strategy committee. He authored more than 100 cited papers and holds 11 U.S. patents. He was elected IEEE fellow in 1994, and served on several IEEE sponsored conference program committees, and is currently vicechair of the technical field awards council and a member of the awards policy and portfolio review committee. Dr. Stork was born in Soest, The Netherlands, and received the Ingenieur degree in electrical engineering (EE) from Delft University of Technology, Delft, The Netherlands, and holds a PhD in EE from Stanford University. 8

9 EOS/ESD Association, Inc. Professional Certification EOS/ESD Association, Inc. offers professional certification for ESD control program managers and device design technical specialists. ESD Certified Professional-Program Manager The impact of the ANSI/ESD S20.20 ESD control program standard on the global industry has been extraordinary. As a result, EOS/ESD Association, Inc. recognizes the need to offer a certification program for individuals that are involved in designing, implementing, managing, and auditing ESD control programs in their facilities. The program manager certification program serves that purpose. In addition, the needs of the technical community for certification of various technical specialists are apparent. Requirements for certification include attending required prerequisite tutorials and passing a final exam. All of the prerequisite courses cannot be completed by attending only the 2018 Symposium. Details of the certification program are also available at the registration desk. The preferred tutorial sequence for the program manager curriculum is: COURSE TITLE FACE TO FACE TUTORIAL ONLINE 1 FC100: ESD Basics for the Program Manager Symposium, Sunday, Sept. 23 FC101: How To s of In-Plant ESD Auditing and Evaluation Measurements 2 Symposium, Monday, Sept FC110: Cleanroom Considerations for the Program Manager Symposium, Thursday, Sept. 27 Online Academy 4 FC120: Air Ionization Issues and Answers for the Program Manager Symposium, Monday, Sept. 24 Online Academy 5 FC200: Packaging Principles for the Program Manager Symposium, Sunday, Sept. 23 Online Academy 6 FC210: ESD Standards Overview for the Program Manager Online Academy DD/FC130: System Level ESD/EMI: Testing to IEC and Other Standards 7 Symposium, Sunday, Sept. 23 Online Academy 8 FC215: Device Technology and Failure Analysis Overview Symposium, Monday, Sept. 24 Online Academy 9 10 FC380: Electrostatic Calculations for the Program Manager and the ESD Engineer FC340: ESD Program Development & Assessment (ANSI/ESD S20.20 Seminar) Symposium, Sunday & Monday, Sept. 23 & 24 Online Academy ESD Certified Professional-Device Design ESD device design certification was developed for individuals that are involved in designing, testing, characterizing, and implementing improved ESD protection designs. Device design certification demonstrates knowledge, experience, and competency in the area of ESD design and test for device protection. Requirements for certification include attending required prerequisite tutorials and passing a final exam. All of the prerequisite courses are not available in the 2018 Symposium tutorial program. Details of the certification program are also available at the registration desk. The preferred tutorial sequence for the device design curriculum is: COURSE TITLE FACE TO FACE TUTORIAL ONLINE 1 DD110: ESD Basics for Advanced Protection Design Symposium, Sunday, Sept. 23 DD301: SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail 2 Clamp Circuits 3 DD211: EOS/ESD Failure Models and Mechanisms 4 DD102: On-Chip ESD Protection in RF Technologies Online Academy 5 DD200: Charged Device Model Phenomena, Design, and Modeling Symposium, Sunday, Sept. 23 Online Academy 6 DD112: Latch-up Fundamentals Online Academy 7 DD300: Circuit-Level Modeling and Simulation of On-Chip Protection 8 DD302: Troubleshooting On-Chip ESD Failures 9 DD120: Device Testing--IC Component Level: HBM, CDM, MM, and TLP 10 DD311: Impact of Technology Scaling on ESD High Current Phenomena and Implications for Robust ESD Design 11 DD220: Transmission Line Pulse (TLP) Basics and Applications Symposium, Monday, Sept. 24 Symposium, Sunday, Sept. 23 Symposium, Thursday, Sept DD/FC130: System Level ESD/EMI: Testing to IEC and other Standards Symposium, Sunday, Sept. 23 Online Academy ESDA Certification Exams The certified professional program manager and device design exams will be held on Friday, September 28. To take the exam, applicants must have a registration form on file with EOS/ESD Association, Inc. headquarters complete with a $50 filing fee prior to the Symposium. Applicants must also have completed all required courses and had their eligibility verified by EOS/ESD Association, Inc. An exam fee of $60 is applicable (in addition to the filing fee). Please note: each of the test sections include essay questions that require a good understanding of English. Up to 50% of the grade in each section may involve essay and short written answers. The exam is open book. You may bring any reference materials, including, but not limited to, books, standards, and tutorial notes. You may also bring a calculator and computer. No cell phones, internet connections, or sharing of reference materials is allowed. 9

10 TUTORIALS: SUNDAY & MONDAY, SEPTEMBER FC340: ESD Program Development and Assessment (ANSI/ESD S20.20) 8:00 a.m. - 5:00 p.m. Ron Gibson, Advanced Static Control Consulting; John T. Kinnear Jr., IBM Corporation Certification: PrM This seminar provides instruction on designing and implementing an ESD control program based on ANSI/ESD S The course provides participants with the tools and techniques to prepare for an ESD facility audit. This two-day course is an ESDA certification requirement for in-plant auditors and program managers who are working toward professional ESD certification. The following topics are covered in this course: Overview of ANSI/ESD S20.20 How to approach an assessment Administrative elements ESD program assessment ESD program techniques for different applications Technical elements Overview of the assessment process The audit checklist and follow-up questions It is recommended that the ESD Program Development and Assessment (ANSI S20.20) be taken after the certification candidate has taken most of the other program manager related tutorials. TUTORIALS: SUNDAY, SEPTEMBER 23 FC100: ESD Basics for the Program Manager 8:00 a.m. - 5:00 p.m. Ted Dangelmayer, Terry Welsher; Dangelmayer Associates, LLC. Certification: PrM This tutorial provides the foundation material for understanding electrostatics and ESD and their role in the manufacturing and handling of ESD sensitive devices. The fundamental properties of charge, electric fields, voltage, capacitance, and current are discussed with a view towards understanding key electrostatic phenomena and electrical processes. These include charge generation and decay, material properties, and induction. An overview of device failure mechanisms is presented, including how these models impact ESD control programs. Finally, the course provides an overview of ESD control procedures during handling and manufacturing and an overview of ANSI/ESD S20.20 program requirements. This full day course is required for those in-plant auditors and program managers who are working toward professional ESD certification. The presentation includes many in-class demonstrations, videos, and animated slides. Some sample topics covered in this course are: Definitions and relationships among important electrical and mechanical properties Causes of charge generation and decay Field effects and voltages Role of capacitance in ESD (Q=CV) Overview of key measurements including common pitfalls of some measurements Review of ESD failure models Understanding and demonstrating electrostatic induction Utility and limitations of air ionization Basic goals of ESD controls Properties of effective ESD control products and materials Overview of ANSI/ESD S20.20 ESD program development requirements Customized, full color tutorial notes will be provided to each tutorial registrant. 10

11 TUTORIALS: SUNDAY, SEPTEMBER 23 DD110: ESD Basics to Advanced Protection Design 8:00 a.m. - 12:00 p.m. Charvaka Duvvury, ESD Consulting, LLC Certification: DD This course gives a comprehensive overview from ESD basics to ESD on-chip design principles, covering up to the latest silicon technologies appealing to a variety of engineers from design to process technology, and failure analysis to quality. The attendee will have an in-depth understanding of the principles of ESD device design along with a full perception of what it takes to address almost every kind of design scenario, how to apply rules of thumb for successful on-chip design, knowledge of lessons learned from case studies, and empowerment to communicate with customers on ESD quality issues. In its complete ESD overview, the course offers emphasis on on-chip protection methods including an understanding of any interactions to the eventual system protection. DD200: Charged Device Model Phenomena, Design, and Modeling 8:30 a.m. - 12:00 p.m. Michael Chaine, Micron Technology, Inc.; Melanie Etherton, NXP Semiconductors Certification: DD This course teaches basic ESD circuit design concepts and ideas required to design ESD protection for charge device model (CDM) ESD tests. The course covers a brief history of CDM ESD development, charge and discharge physics, characterization methods, CDM failures mechanisms, and CDM design-in strategies. CDM ESD circuit design approaches and simulation setups for CDM failure debugging are presented in this tutorial on the basis of case studies. Insight into CDM circuit simulation requirements and physical aspects of the CDM ESD phenomenon that are important for reproducing the event with circuit simulation will be taught, and modeling approaches for CDM specifi c device physical effects necessary for accurate circuit simulation will be introduced. This course also teaches methods for simplifi ed CDM circuit simulations where detailed information is either not available or too complex to simulate. The course focuses on what type of circuits fail during a CDM discharge event and teaches the different types of ESD design circuit strategies that can be applied to protect those circuits. This class covers basic to advanced topics for CDM ESD design, but the student is assumed to already have a basic understanding of the CDM test method. DD/FC130: System Level ESD/EMI: Testing to IEC & Other Standards 8:30 a.m. - 12:00 p.m. Jeff Dunnihoo, Pragma Design, Inc. Certification: PrM, DD This tutorial is intended to help those tasked with testing products to system level ESD standards by providing first an overview of how real-world system ESD events are simulated in different standards and testers in general, and then provide detailed information on IEC , the most widely used standard. This introduction will highlight the similarities and differences between IEC, ANSI, Telcordia, and some automotive ESD standards. We will answer common questions regarding test setups, test points, and procedures, and address key issues, including: 1) differences between verification and calibration and when is each required; 2) test equipment requirements, the test environment, ground connections, return paths, and ground plane effects. 3) Testing procedures with demonstration on actual products, how the tester and procedure affects test results, and problems with test result variations due to simulator influences; 4) definitions of testing failure criteria for the product; 4) what points need to be tested and why, guidance on determining operator accessible points and ports, exempted points and ports, and what to do around connectors and connector pins. 5) ANSI and other ESD standards, the drive toward harmonization with IEC, the scope of different standards, and why they are unlikely to converge. This system level ESD tutorial will cover different perspectives on ESD as applied to electronic systems from the user s, the designer s, and even the designer s competitor s points of view. FC200: Packaging Principles for the Program Manager 8:30 a.m. - 12:00 p.m. David E. Swenson, Affinity Static Control Consulting, LLC Certification: PrM Shipping electronic parts within a factory, to another factory, distributor, or to an end-user has always been an area of uncertainty within the manufacturing process. To provide clear-cut information on what type of controlled packaging should be used in any situation, EOS/ESD Association, Inc. released a comprehensive revision of the obsolete industry standard EIA The newer document, ANSI/ ESD S541, is the focus of this inclusive session. It provides information and guidance, as well as material specifi cations, to assist in the design and implementation of a packaging plan for use within an ANSI/ESD S20.20 based ESD control program. Current and newly released test method standards suitable for packaging material evaluation will be described. Course credit applies to the ESD program manager certifi cation curriculum. Previous attendance at the FC100: ESD Basics and FC101: How To s tutorials are highly recommended. Customized, full color tutorial notes will be provided to each tutorial registrant. 11

12 TUTORIALS: SUNDAY, SEPTEMBER 23 FC165: Novel Methods for Fixing ESD Issues in the Factory for Both Electronics & Explosive Products 8:30 a.m. - 12:00 p.m. Jay Skolnik, Skolnik Technical Training This class will be a 3-hour tutorial on ESD control for explosives and other energetic materials, introducing the students to the differences of ESD damage of electronics versus energetics. It will discuss the various energy levels and types of discharges which can cause catastrophic or latent failures. Enlightening demonstrations and case histories will be included to illustrate practical, real-life situations of past ESD-induced failures of energetic components and methods to prevent them, as well as explanations of the use of ESD mitigation in the work environment. Upon tutorial completion, the students should be able to understand ESD and the prevention of ESD failures be applying the proper mitigation & control techniques, as well as safely work with explosive applications while ensuring human safety, preventing catastrophic health hazards, injuries, and severe damages. DD201: ESD Protection and I/O Design 1:00 p.m. - 4:30 p.m. Michael Stockinger, NXP Semiconductors This tutorial is intended to provide the attendees with the tools to take a device and circuit level understanding of ESD protection methods and implement them effectively in I/O designs for CMOS bulk technologies. Beginning with a review of common ESD protection strategies, this course will focus more directly on how to build ESD-robust I/O cells and how to integrate them on a full chip. The tutorial will cover various types of I/O pads including analog, RF, and digital pads. Different types of ESD protection strategies and their usage in I/O pad cells will be described, for example, rail clamp, self-contained, and SCR based protection schemes. This course will also discuss the decisions and challenges which ESD and I/O designers typically face when designing I/O pads. More complex ESD solutions will also be described such as stacked rail clamps, ghost rails, and protecting signals that can swing below ground or above the supply. Finally, this tutorial will touch on various supply schemes including multiple power domains and isolated grounding schemes. It will end with discussing pad ring construction aspects for both wire-bond and flip-chip packages. DD204: ESD Design in HV Technologies 1:00 p.m. - 4:30 p.m. Lorenzo Cerati, STMicroelectronics; Yiqun Cao, Infineon Technologies This tutorial gives an introduction to ESD design in high voltage technologies for integrated circuits with pin voltages from 12 volts upwards. After a short introduction of typical applications and requirements, an overview of different technologies and the typical device portfolios in these technologies will be given. Different ESD protection concepts are introduced, analyzing advantages and disadvantages of the various possible approaches to implement ESD networks (diodes, snapback devices, active clamps, etc.). Finally, HV technology and design related challenges regarding ESD protection are discussed, with a special focus on the formation of parasitic bipolar devices and the impact on the circuit s ESD performance. The attendee will gain a good basic knowledge of the main characteristics of HV technologies, the different ESD protection concepts, and ESD protection challenges that are specifi c for HV technologies. This will be a help for understanding and further development of HV ESD protection. An extensive literature list is provided for further study of various subjects regarding HV ESD. NEW FC365: Practical Applications of Ionization 1:00 p.m. - 4:30 p.m. David E. Swenson, Affinity Static Control Consulting, LLC Ionization is a powerful tool in the toolbox of an ESD control practitioner. Our half-day tutorial, Ionization Issues and Answers for the Program Manager goes into depth about the physics of ionization, and general applications. This tutorial builds on the fundamentals and provides added information about applications of ionization that go beyond those mentioned in the original tutorial. The introduction part of this tutorial begins with a review of the physics of ionization before entering the discussion of applications. Ionization is used in a wide variety of industrial applications to reduce charge on plastic and paper films, extrusion processes, pharmaceutical and other powders, petrochemical processing, printing and graphic arts, as well as the wide variety of electronic component and equipment production processes. Numerous demonstrations will help demonstrate the power of ionization to reduce charges on materials. In addition, it is necessary to understand the limitations of ionization and recognize where it is useful and where it is not. Customized, full color tutorial notes will be provided to each tutorial registrant. 12

13 TUTORIALS: SUNDAY, SEPTEMBER 23 FC370: Basics of EMI and EOS in Manufacturing Environment and Their Mitigation 1:00 p.m. - 4:30 p.m. Vladimir Kraz, OnFILTER High-frequency noise, known as EMI - electromagnetic Interference - causes a number of problems in an industrial environment, as well as in other applications - medical, R&D, data centers, and alike. These problems are divided into two main categories: interference with normal operation of equipment and EMI-caused electrical overstress (EOS). EMI leads to erratic operation of equipment, errors in test and measurements, and can even pose a safety hazard. EOS is the number one cause of damage to IC components according to Intel. Most companies have ESD under control; however, EOS is seldom addressed. Failure analysis often misdiagnoses EOS-caused failures as caused by ESD. Factories today do not have adequate knowledge to deal with the critical to yield and quality EOS exposure. This half-day course familiarizes factory engineers, technicians, and managers with the phenomenon of EMI and EMI-caused EOS, its quantifi cation, problem diagnostics, and mitigation basics. Course Objectives: Understanding of EMI phenomenon Understanding of EOS and how it is caused by EMI Practical skills in EMI measurements at the factory Understanding of basics of EMI mitigation Understanding of basics of EMI audit Participants of this course will learn practical fundamentals of EMI, how to manage EMI and EOS in their factories, and will be able to implement the new knowledge in practice. DD311: Impact of Technology Scaling on Components High Current Phenomena and Implications for Robust ESD Design 1:00 p.m. - 4:30 p.m. Gianluca Boselli, Texas Instruments Certification: DD TUTORIALS: MONDAY, SEPTEMBER 24 FC101: How To s of In-Plant ESD Auditing and Evaluation Measurements 8:30 a.m. - 4:30 p.m. Stephen Halperin, Stephen Halperin & Associates, Ltd. Certification: PrM This program reviews the evaluation and periodic verification (audit) measurement procedures for the technical requirements specified in the ANSI/ESD S20.20 ESD program development standard. Detailed explanation of instruments, fixtures, and accessories function and usage are provided. Then, the details of How to measure are explained and demonstrated. Measurements include those listed in Table 1: Grounding/Equipotential Bonding Requirements; Table 2: Personnel Grounding Requirements; and Table 3: EPA/ESD Control Items. These recommended measurement procedures confirm the proper operation and use of ESD control products and materials selected as part of a facility s S20.20 ESD control program. Some sample topics covered in this course are: ANSI/ESD S20.20 Technical Control Requirements Program Manager s Approach to Instrumentation and Applications Testing Ground Circuits and Assessing Connections Essential Resistance Measurement Procedures and Concerns Electrostatic Field and Voltage Measurements Personnel Grounding Considerations vs. ESD Control Points Product Installation Baseline Measurements Evaluation, Acceptance, and Audit Procedures for: Ground Systems, Floors, Worksurfaces, Equipment, Personnel Grounding, Garments, Materials, Production Aids, Packaging, and Ionization Devices Electrostatic Analysis Measurements including Worksurface Suppression, Footwear/Flooring, and This advanced tutorial will focus on high-current behavior of stand-alone components, with the aim of optimizing effectiveness of ESD clamp devices (irrespectively of their schematic implementation) and maximizing the ESD SOA (Safe Operating Area). Components in both Analog and Digital technologies will be discussed, with emphasis on technology trends. This class is intended for individuals who have taken the basic on-chip protection class and are familiar with the basic device physics for both ESD and latch-up. Customized, full color tutorial notes will be provided to each tutorial registrant. 13

14 TUTORIALS: MONDAY, SEPTEMBER 24 DD231: ESD System Level: Physics, Testing, Debugging of Soft and Hard Failures 8:30 a.m. - 12:00 p.m. David Pommerenke, University of Missouri-Rolla The tutorial is an expanded version of the previous DD231 tutorial on system level ESD. The main difference is the addition of many experimental demonstrations, update of information, and in-depth discussion on problems of the IEC testing, with examples on how to perform this testing and obtain the best possible results and documentation. About half of the time will be spent on experimental demonstrations. Topics will include: ESD physics: charging and discharging. System level ESD testing System level soft failure mechanisms and debugging Design for avoiding ESD problems FC120: Air Ionization Issues and Answers for the Program Manager 8:30 a.m. - 12:00 p.m. Arnold Steinman, Electronics Workshop, Certification: PrM The primary method of static charge control is direct connection to ground for conductors, static dissipative materials, and personnel. Air ionization is also part of a static control program to deal with the problems of isolated conductors and insulating materials. This seminar is a basic course on ionizers, providing an introduction to their use, as well as application information. It examines common problems caused by static charge and the need for ionizers in a static control program. Types of ionizers, their use environments, and performance test methods using the Ionization Standard will be demonstrated. Installation, safety, maintenance, and contamination issues will be presented. Finally, case histories will be analyzed illustrating the use of ionizers in a variety of work environments. DD100: ESD Circuits 8:30 a.m. - 12:00 p.m. Gene Worley, Qualcomm, Inc. This tutorial will focus on a number of clamp approaches including BigFETs or RC clamps, snap-back NFETs, diodes, SCRs including HV SCRs, low capacitance clamps methods including those for MOSFET based LNAs and RF transceiver switches, and cross domain clamping. Spice simulations and simple models where applicable will be used to design and analyze circuit performance. Models include HBM, CDM, and IEC sources, gate pull requirements for dynamically lowering snap-back thresholds, and diodes. Gate pull for snap-back NFETs will include cascade and stacked NFETs. The need for NQS MOSFET models will be discussed with respect to CDM simulations. Operational characteristics of diodes will be examined including simple models and turn on delay. Diode types to be examined include STI, gated, and gated with LDD block. Protecting RF transceiver switches will be studied and will include spice simulations and design of low capacitance snap-back NFETs. Cross domain analysis will feature SPICEbased gate oxide rupture models and design requirement for secondary clamps including secondary clamps for LNAs. NEW DD/FC250: What Information Needs to be Exchanged for Potential EOS Problem 8:30 a.m. - 12:00 p.m. Reinhold Gaertner, Infineon Technologies; James Roberts, Continental Corporation EOS-like damages represent a significant percentage of components returned by the OEM s to tier1 and semiconductor manufacturers for comprehensive failure analysis in the automotive industry. There is generally a requirement from the OEM to conduct a detailed investigation to determine the root cause of the failure; however, commonly this cannot be done due to missing information and poor communications but blocks a lot of capacity. This tutorial presents information based on case studies why it is not possible to find the root cause for an EOS-like damage without an information sharing between all tier levels. Based on the new guideline (to be published by WG27) a two level support will be introduced based on an information sharing between the OEM, tier1 and semiconductor manufacturers that can lead to a higher chance to identify the root cause of the damage and allows to focus on the important topics. Customized, full color tutorial notes will be provided to each tutorial registrant. 14

15 TUTORIALS: MONDAY, SEPTEMBER 24 NEW DD115: Latch-up Basics and Testing 8:30 a.m. - 10:00 a.m. Marty Johnson, Texas Instruments, Inc. This tutorial will introduce the participant to the basics of latch-up stress testing.the course will cover basic latch-up theory, basic latch-up mitigation techniques, the JEDEC Latch-up Standard (JESD78) and discuss the effects of the standard on stress testing methodology. Also, there will be a discussion of possible differences in set-up when stress testing between digital, mixed signal and analog products. Examples of these set-ups will be described and discussed to aid the student better apply the methods in their stressing environment. Interpretation of the stress data will be described. The future of the standard will also be discussed and how that may impact the philosophy of stressing. This tutorial can be very helpful for a variety of people in the semiconductor industry including circuit designers, product engineers, test engineers, failure analysts, quality / reliability engineers and technicians supporting latch-up stressing. DD117: TCAD Fundamentals 10:30 a.m. - 12:00 p.m. Kai Esmark, Infineon Technologies TCAD (technology computer aided design) tools have become an indispensable utensil for the semiconductor industry. The possibilities to analyze, predict and optimize a certain semiconductor device behavior through modeling semiconductor fabrication (Process TCAD) and semiconductor device operation (Device TCAD) are countless. This includes the area for ESD and Latch-up development, as early access to fundamental device parameters under very high current density and high temperature transients is the key to overcome the conceptual problem of concurrent engineering for ESD engineers. This tutorial serves as a basic introduction into TCAD tool chain including process and device simulation as well as the creation and integration of compact models for mixed more simulation. Focus points are the capabilities but also limitations of these tools, like the requirements for a 2D/3D simulation approach and the validity of the models describing the fundamental physics, especially in the high temperature regime. DD340: Integrated ESD Device and Board Level Design 1:00 p.m. - 4:30 p.m. Harald Gossner, Intel Deutschland GmbH The tutorial is a hands-on training course for performing a simulation based optimization of PCB ESD protection design and provides deep understanding of the relevant performance criteria both of TVS diodes and IO circuits. The presented method follows the system effi cient ESD design (SEED) approach as recommended by the Industry Council on Target Levels and JEDEC. The method allows the achievement of correct fi rst time PCB builds and reduces the respin effort for boards and ICs. Based on a TLP characterization of SoC interface circuits and TVS diodes, simulation models for impedance and clamping behavior, as well as failure threshold, are extracted. These are used to assess design solutions by transient simulations. This is showcased by real world examples. REVISED DD300: Circuit-Level Modeling and Simulation of On-Chip Protection 1:00 p.m. - 4:30 p.m. Elyse Rosenbaum, University of Illinois at Urbana-Champaign Certification: DD This tutorial addresses modeling of on-chip ESD protection devices and simulation of ESD protection networks. The primary focus is SPICE-type simulation with compact (physics-based) models but a general survey of modeling approaches and simulation techniques will also be provided. The physical operating principles of commonly-used ESD protection devices will be examined. The high-current characteristics and transient responses of those devices will be explored to ascertain what behaviors should be captured by a model intended for circuit-level simulation of ESD. Specific examples of model implementations will be provided. Techniques for circuit-level modeling of self-heating will be presented. Parameter extraction and model scalability will be addressed. This tutorial assumes some familiarity with device physics. It is directed toward persons with interests in semiconductor device physics, electronic design automation, and on-chip ESD protection circuit design. Customized, full color tutorial notes will be provided to each tutorial registrant. 15

16 TUTORIALS: MONDAY, SEPTEMBER 24 FC215: Device Technology and Failure Analysis Overview 1:00 p.m. - 4:30 p.m. Jim Vinson, Intersil Corporation Certification: PrM This tutorial is designed to give an overview of ESD protection technology and design, as well as an overview of the debug techniques used when a circuit fails to meet ESD performance requirements. The three major areas addressed are 1) a general overview of ESD; 2) circuit protection techniques; and 3) failure analysis. Failure analysis is the key to identifying and correcting weaknesses in ESD designs. The tutorial is NOT intended to turn the student into an ESD device or circuit designer nor a failure analyst. Rather, it is meant for program managers and other support personnel who are involved in the product development process to gain a better understanding of the language and challenges encountered supporting ESD robustness in new designs. After completing this tutorial, the student will be exposed to the key specifi cations governing ESD robustness and the common device architectures used to provide that robustness. The tutorial will include real world examples of protection designs and electrical characterization of those designs, as well as go through the tools and techniques used to debug a design. DD/FC330: Control of Charged Board Event (CBE) 1:00 p.m. - 2:30 p.m. Pasi Tamminen, Tampere University of Technology Charged board event (CBE) is an ESD phenomenon where printed circuit boards and other electrical systems are charging up and create stress on the components or ICs mounted on the board when the board or system is grounded. In this tutorial the CBE phenomena and CBE control methods are presented in detail. The tutorial includes CBE failure cases, measurement and simulation methods, and discusses how to use measured discharge parameters to evaluate system level CBE risk in electronics handling. The tutorial provides methods to detect, measure, and mitigate CBE risks in electronics handling. DD317: ESD Challenges in Advanced FinFET and Gate-All-Around Nanowire CMOS Technologies 1:00 p.m. - 2:30 p.m. Shih-Hung Chen, imec Bulk FinFET has been a mainstream CMOS technology in sub-20 nm nodes because of improved channel electrostatic and leakage control. ESD reliability has been investigated in bulk FinFET and is strongly impacted by newly introduced process options in these advanced technologies. The process options include self-align double patterning (SADP) lithography, local interconnect (LI) defi ned contact scheme, and S/D epitaxial growth in different process modules. The process options have impacts on ESD failure level, clamping voltage and turn-on effi ciency. In addition, higher supply voltages (e.g., 1.8 volts or 3.3 volts) are still required in I/O interface circuits and some analog circuits in bulk FinFET technologies. The I/O transistors concerning latch-up (LU) prevention are also infl uenced by the specifi c process options in sub-20 nm nodes. Next to the FinFET technology, a gate-all-around (GAA) nanowire (NW) technology is a promising candidate for sub-10 nm nodes. This new device architecture will also bring impacts on ESD device characteristics. In this tutorial, we will look at the infl uence of the device architectures and the corresponding process options on ESD device characteristics in the FinFET/GAA NW technologies. 3D TCAD simulations bring an in-depth physical understanding of the ESD current conduction and failure mechanism in the ESD protection devices. After this tutorial the attendees will have a clear picture of: The process options in the FinFET and GAA NW technologies The process options impact ESD device characteristics The process options impact LU immunity The ESD challenges in future CMOS technology nodes FC201: ESD - A Surprisingly Frequent Root Cause of Device Failure 3:00 p.m. - 4:30 p.m. Ted Dangelmayer, Dangelmayer Associates LLC While most companies are acutely aware of the hazards of ESD, few are aware of just how pervasive ESD failures actually are. Likewise, many ESD Program Managers have difficulty securing adequate management support. This tutorial will shed light on multiple sources of ESD damage and the circumstances where ESD failures dominate. Recent studies into the misdiagnosis of EOS failures suggest that ESD damage may, in fact, occur much more often than previously realized especially at the circuit board level. This fact is a compelling justification for strong management support. The student will also learn which are the most frequent ESD failure mechanisms among CDM, HBM and MM and why. The student will also learn about the best practices for prevention for these recently recognized sources of ESD damage. Customized, full color tutorial notes will be provided to each tutorial registrant. 16

17 TUTORIALS: MONDAY, SEPTEMBER 24 TUTORIALS: THURSDAY, SEPTEMBER 27 NEW Emerging Topic: Technology and ESD Challenges Towards 7nm 3:00 p.m. - 4:30 p.m. Robert Gauthier, GLOBALFOUNDRIES The tutorial will provide to the attendees an overview of the ESD challenges across different technology architectures as device/technology scaling continues down to the 7nm node. Three major technology families are reviewed. First, we will cover the most common bulk CMOS device scaling, from planar to FinFet based devices. This is followed by the traditional PD-SOI planar devices which are scaled to SOI FinFET based devices. Finally, we will review fully-depleted (FD) SOI devices. For each technology family we will show how the ESD device and design window is impacted by technology scaling. Also the key figure of merit (FOM) device parameters are reviewed. Finally, special topics such as ESD challenges in 3D packaging will be reviewed. FC170: ANSI/ESD S20.20 ESD Program Assessment for Internal Auditors and Supplier Quality Engineers 8:30 a.m. - 4:30 p.m. Ron Gibson, Advanced Static Control Consulting; John T. Kinnear Jr., IBM Corporation This class has been designed specifically for those individuals who are responsible for: Performing internal company ESD assessments based on ANSI/ESD S20.20 Conducting a pre-assessment of their facility prior to an external 3rd party assessment Assessing the ESD control programs of their suppliers This course will use the checklist used by ESDA certified auditors as the basis for the class. However, this class will delve into the meaning behind each of the audit checklist questions in greater detail than is currently found in either the ESD Association registrar certification training or the ANSI/ESD S20.20 ESD program design seminar. After taking this class the student will be able assess a process and determine whether or not it meets the requirements of ANSI/ESD S Note: Familiarity with performing assessments is recommended for anyone planning on taking this course TUTORIALS: TUESDAY, SEPTEMBER 25 Calculations and ESD Scenarios Review for ESD Program Manager Exam Preparation (STUDY SESSION) 5:00 p.m. - 6:00 p.m. Stevan Hunter, ON Semiconductor Intended for those taking the ESD certified professional program manager exam. Review of the basic physics, calculations, and some ESD scenarios. (Includes problem solutions for an accompanying handout, available at registration). DD260: Design for EOS Reliability 8:30 a.m. - 12:00 p.m. Charvaka Duvvury, ESD Consulting, LLC During the design of on-chip protection and latch-up immunity, the consequences to EOS damage susceptibility are often overlooked. This class aims to fi rst clearly establish the nature of EOS and some of the common causes for unintended EOS, followed by the on-chip IC design styles that can lead to EOS damage and customer returns. By way of illustrative examples and case studies, these potential issues are highlighted. These include the designs in low voltage CMOS, mixed voltage technologies, analog designs, and high voltage designs. Some mention of automotive applications leading to EOS and the automotive perspective will also be covered. Finally, the design rules to follow for EOS mitigation; as well as on-going communication tips with customers to achieve these objectives, will be reviewed. The course aims to give a clear understanding of EOS events, the defi nition of EOS related to on-chip design principles, design improvements to overcome EOS return rates, check lists for EOS avoidance, and tips for customer communications. Customized, full color tutorial notes will be provided to each tutorial registrant. 17

18 TUTORIALS: THURSDAY, SEPTEMBER 27 FC110: Cleanroom Considerations for the Program Manager 8:30 a.m. - 12:00 p.m. Chris Long, IBM Certification: PrM Cleanrooms and clean environments are enabling technologies required for the manufacturing of many products that have exacting contamination control requirements in order to achieve defi ned yield and reliability targets. Clean manufacturing is required in the semiconductor, hard disk drive, fl at panel display, and pharmaceutical industries, to name a few. Requirements of cleanroom and clean environments, and tooling therein, result in low humidity levels, low surface contamination levels, use of process-required insulators, and a lack of natural ions in the controlled environment. These factors can contribute to the development of elevated static charge levels in close proximity to sensitive products, presenting both a contamination and electrostatic discharge exposure. This tutorial will provide a detailed review of the following concepts: Cleanroom and clean environment function Airborne particle classifi cation standards Cleanroom compliance monitoring test methodologies Electrostatic attraction relation to airborne and surfacecontamination Electrostatic discharge concerns Cleanroom static charge generation challenges and control methodologies In addition, several case studies of static charge control issues in clean environments will be presented. NEW DD150: Introduction to RF ESD Design 8:30 a.m. - 12:00 p.m. Kathleen Muhonen, Qorvo REVISED FC361: ESD Controls for CDM and Ultra-Sensitive Devices and Circuit Boards 8:30 a.m. - 12:00 p.m. Terry Welsher, Dangelmayer Associates, LLC Advanced ESD Controls and Auditing Measurements for CDM & Class 0 (ultra-sensitive) devices and Circuit Boards are not well known and there are many technical and strategic pitfalls that must be avoided. Industry definitions (threshold levels) for Class 0 will be described and the history of their use will be reviewed. The Class 0 category is broken down into sub-categories of increasing risk. Students will learn how to make valid measurements, avoid common pitfalls, and how to use this data to successfully handle Class 0 sensitivities. Advanced measurements will be described including event detection and high speed current measurements. Students will learn when each measurement type is useful. Compelling case studies will illustrate these techniques and the success they produce. ESD Control procedures for Class 0 manufacturing require customization, attention to detail and a full understanding of the technology. Thus, each company will need to develop a Class 0 ESD subject matter expert (SME) to ensure the correct and cost effective counter measures are taken. SOPs (Special Operating Procedures) developed by SMEs will be discussed that have proven to virtually eliminate Class 0 failures. This tutorial will be highly interactive with live demonstrations, in-plant photographs, and video clips. Students will be encouraged to ask questions and actively participate in the discussions. References to technical literature on ultra-sensitive devices will be included. This tutorial is an introduction to RF concepts and RF ESD clamp design. It is intended for ESD engineers who do not have an RF background to come up to speed on the concepts needed to design effective protection circuits. The RF concepts include impedance matching and smith chart basics. RF amplifier operation and load line basics are presented to give a foundation for the RF ESD protection circuit design. The tutorial will also touch briefly on RF switches and filters. The second half of the tutorial will focus on how to design an ESD clamp for an RF application. Concepts will be presented such as calculating the turn-on voltage of the clamp such that it will protect the part but not turn on during normal, RF operation. A clamp s parasitics also needs to be considered in an RF application so that the parasitics do not degrade the product s performance. Finally, some testing tools will be reviewed with respect to testing RF products. The challenges will be highlighted and different testing practices that are used in HBM, TLP and IEC testing of RF products will be reviewed. Customized, full color tutorial notes will be provided to each tutorial registrant. 18

19 TUTORIALS: THURSDAY, SEPTEMBER 27 NEW DD/FC165: Design Engineer - Weak Link or Warrior in the ESD Battle? 8:30 a.m. - 10:00 a.m. Ginger Hansel, Dangelmayer Associates, LLC Design Engineers strive to incorporate ESD protection into chip designs, but they are often unclear about the best way to handle the physical devices. The Industry Council on ESD Targets documented a need to lower both the HBM and CDM thresholds with the confidence that factories already had the appropriate ESD control programs in place. However, many engineering labs do not understand or follow industry ESD guidelines and are unaware of the potential jeopardy created by these lower thresholds. Anyone doing device testing, characterization, TLP stress testing, board level analysis or upgrading their own computer should know basic ESD control techniques. This seminar will include practical ESD control tips for engineering labs as well as how to set up and monitor a comprehensive ESD control program. Real world examples will show the increased ESD risk of Charged Board Events (CBE), the surprising damage due to hand tools and how to use event detectors to identify ESD threats. You ve spent a lot of effort doing careful designs now take good care of your valuable test chips and prototype engineering samples. DD213: ESD, EOS, and Latch-up Failure Analysis for Designers 10:30 a.m. - 12:00 p.m. Jim Vinson, Intersil Corporation This tutorial will introduce the student to the fi eld of failure analysis (FA) as it is performed on ESD, EOS, and latch-up failures. This tutorial is not trying to make the student into a failure analyst. This takes 3-5 years of mentoring to cultivate. The emphasis will be on understanding the diagnostic process and applying the correct set of tools to the failure with the ultimate goal of determining a corrective action to improve the product s robustness to these stresses. Examples will range from discrete clamp debug to FA on a complex circuit. FA combines the skill set of a detective, designer, and device physicist to understand what has happened to cause failure. DD220: Transmission Line Pulse (TLP) Basics and Applications 1:00 p.m. - 4:30 p.m. Evan Grund, Grund Technical Solutions, Inc. Certification: DD This tutorial will cover the basics of TLP including underlying theory, the types of TLP systems available, and how I-V curves are extracted from TLP pulses. The tutorial uses examples to show how fundamental device parameters can be measured with TLP. These parameters allow the ESD engineer to understand a technology s properties which can be used to design successful ESD protection circuits. The student will gain an understanding of the purpose of TLP measurements, how TLP relates to HBM and CDM, fundamentals of how TLP systems work, including impedance and refl ections, types of TLP systems, importance of load lines, adaptive ranging, TLP calibration, time dependence from TLP, and biased TLP measurements. The tutorial will present examples of TLP use for nmos transistors, diodes, oxides/capacitors, and power supply clamps, as well as time dependent TDR-O and VF-TLP examples. FC262: Electrical Fields and Particles - Practical Considerations for the Factory 1:00 p.m. - 4:30 p.m. David E. Swenson, Affinity Static Control Consulting, LLC ANSI/ESD S20.20 recommends that process essential insulators with a measured electrical field strength of >2000 volts at 1 inch should be kept a minimum of 12 inches from ESD susceptible items. In addition, for close proximity or contact, the standard requires that insulators have an electric field of <125 volts at 1 inch. Just what are the practical considerations of these statements? What is the size of a charged object and magnitude of an electric field that imposes a real risk? The goal of this tutorial is to show, by demonstration, the fi eld strength and resulting induction ability from different sized objects. Electric fields are the major contributor (beyond gravity) to attraction of particles to surfaces. The science of particle attraction, adhesion and particle removal is very complex but it is important to have a fundamental understanding if your production processes involve cleanliness of surfaces. This tutorial will cover the important considerations of particle dynamics. The audience should gain a practical perspective of size and distance as related to charged objects, electrical fields, induction, and the interaction of electric fields with airborne particles. Customized, full color tutorial notes will be provided to each tutorial registrant. 19

20 TUTORIALS: THURSDAY, SEPTEMBER 27 FC150: Hands-on ESD Measurements & Instruments-Uses and Pitfalls 1:00 p.m. - 4:30 p.m. Ginger Hansel, Dangelmayer Associates, LLC Accurate data is the foundation of effective ESD program management. This hands-on tutorial will explain and demonstrate the proper use of ESD test equipment such as static locators, resistance meters, charge plate monitors, and event detectors. We will examine pitfalls of using these common instruments that can result in an incorrect representation of the ESD risk. For example, static locators can give misleading readings if the effects of voltage suppression are not taken into account. We will also discuss the effective use of ionization since ionizers that are not measured, maintained, and located correctly may contribute ESD hazards to the work area. Each student will participate in class exercises to perform these tests. The hands-on experience is the best way to understand the seriousness of the pitfalls and the benefits to taking the proper precautions. What you learn will help you avoid frequent auditing problems and improve your compliance verification program. You will also practice some key measurements from the ESD Association technical report ESD TR FC360: Electrical Overstress (EOS) in Manufacturing and Test 1:00 p.m. - 4:30 p.m. Terry Welsher, Dangelmayer Associates, LLC Electrical overstress (EOS) is a major cause of device failure in manufacturing and in the field. Despite this, there is relatively little information on the sources of EOS and on prevention practices, particularly for the factory. In this tutorial, the fundamentals of device overstress are reviewed. Relationships among device EOS stressing models, such as the Wunsch- Bell curve, are discussed. The causes of EOS and EOS-like events in manufacturing are described and categorized by source and by stress-type. The difficulties in distinguishing between power-induced EOS and high current ESD events such as charged-board events (CBE) and cable discharge events (CDE) are discussed. Case histories, including failure analysis and root cause determination, are presented and the few relevant industry specifications are reviewed. Customized, full color tutorial notes will be provided to each tutorial registrant. 20

21 TUTORIALS: THURSDAY, SEPTEMBER 27 DD381: Electronic Design Automation (EDA) Solutions for ESD 1:00 p.m. - 2:30 p.m. Michael Khazhinsky, Silicon Laboratories, Inc. The verification of ESD protection networks in modern integrated circuits is a diffi cult challenge due to increasing design and process complexity, higher pin-counts, and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another; across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves, may become damaged as a result of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a signifi cant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the recently released ESDA technical report ESD TR (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development. DD382: Electronic Design Automation (EDA) Solutions for Latch-up 3:00 p.m. - 4:30 p.m. Michael Khazhinsky, Silicon Laboratories, Inc. The verification of latch-up protection networks in modern integrated circuits is a difficult challenge. There are several factors including increasing design and process complexity, higher-pin counts, and the overall computational diffi culties in dealing with large data sets. Traditional latch-up geometrical rule checks using DRC tools can only provide limited verifi cation. These checks are typically focused on layout topology. However, electrical information for latch-up risk areas throughout the chip is not readily available. While DRC checks are still useful at early design stages, relying on conventional DRC latch-up checking exclusively, poses a significant risk of missing hidden latch-up pitfalls. Consequently, a fully automated latch-up rule checking approach analyzing electrical information is highly desired. In this tutorial we will review a typical latch-up prevention fl ow. Then, the dual DRC and Calibre PERC-based latch-up verification flow will be shown. We will then provide an example of identifying latch-up injectors and describe how this information could be used in both a DRC and Calibre PERC based verification flows. Afterwards, the tutorial will introduce the concept of context based checking as it applies to latch-up spacing checks. An example of validating latch-up prevention techniques for the devices in grounded nwell will be shown along with additional latch-up verification case studies related to guard rings and well ties. Customized, full color tutorial notes will be provided to each tutorial registrant. 21

22 Technical Sessions: Tuesday, September 25, Parallel Sessions Exhbitor Showcase 10:00 AM-10:10 AM Ansys, Inc. - Booth 107 Session 1A: 10:10 AM-12:15 PM 1A: Advanced CMOS Moderator: Michael Stockinger, NXP Semiconductors Exhibitor Showcase: 10:00 AM-10:10 AM Barth - Booth 200 Session 1B: 10:10 AM-12:15 PM 1B: Manufacturing I Moderator: Michelle Lam, IBM 1A.1 Design and Optimization of ESD P-Direction Diode in Bulk FinFET Technology You Li, Meng Miao, Robert Gauthier, GLOBALFOUNDRIES We present ESD P-direction STI diode results in advance bulk FinFET technology. The process impacts and design parameters are evaluated in detail. With design optimization, the ESD P-direction STI diode achieves 26% higher performance than C-direction design. 1A.2 An Enhanced DNW-enclosed NMOS in FinFET Technology for Latch-up Improvement Chien-Yao Huang, Yu-Ti Su, Kuo-Ji Chen, Ming-Hsiang Song, TSMC An embedded lightly-doped region (LDR) is proposed to suppress DNW-induced latch-up susceptibility reported in the previous study. The proposed structures in FinFET technology are investigated through TCAD simulation and experiments. LDR shows a significant holding voltage improvement as well as excellent hot-temperature immunity, which are hard to be achieved by conventional methods. 1A.3 Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node Aihua Dong, University of Central Florida; Jie Xiong, University of Illinois at Urbana Champaign; Souvick Mitra, Wei Liang, Robert Gauthier Jr., Alain Loiseau, GLOBALFOUNDRIES ESD design windows for mainstream bulk and SOI planar/finfet technologies across 350nm-7nm node are compared for the first time. 100ns TLP and 1ns vftlp characteristics of Vgox, Vt1, and It2 of various logic and I/O FETs are presented and discussed. Expanding the design window by utilizing series resistance with driver is discussed. 1B.1 Relationship Between Footwear Resistance and Personal Grounding Through Footwear and Flooring Jeremy Smallwood, Electrostatic Solutions Ltd; David E Swenson, Affinity Static Control Consulting, LLC; Toni Viheriäkoski, Cascade Metrology ESD control footwear is qualified using resistance measurements for use in an explosives handling facility. This paper explores the relationship between footwear resistance and the personal grounding performance in terms of measured resistance from body to ground and body voltage generated in a walk test with antistatic and conductive floors. 1B.2 Study of the Discharge Current Created by an Ionizer Stefan Seidl, Friedrich zur Nieden, Reinhold Gaertner, Infineon Technologies AG Ionizers are often used to limit the charging of insulators in an EPA. Unfortunately a simple table top characterization with a charged plate monitor is not sufficient to guarantee safe performance when mounted inside a production machine. In this contribution we present a novel alternative by directly measuring the discharge current of an ionizer. 1B.3 ESD Shielding of Thermoformed Clam Shell Packaging Toni Viheriäkoski, Cascade Metrology; Rita Fung, Richard Wong, Cisco Systems, Inc.; Reinhold Gaertner, Infineon Technologies AG; Jeremy Smallwood, Electrostatic Solutions Ltd; Pasi Tamminen, EDR&Medeso Oy Clam shells may provide better ESD protection than shielding bags. Energy oupling in a near field is generally reduced by preventing a direct connection, decreasing capacitive coupling, and increasing breakdown field strength. A properly qualified shielding bag may have unsuspected weakness in ESD protection due to the low breakdown field strength. 22

23 Technical Sessions: Tuesday, September 25, Parallel Sessions Session 1A: 10:10 AM-12:15 PM 1A: Advanced CMOS (Continued) Moderator: Michael Stockinger, NXP Semiconductors Session 1B: 10:10 AM-12:15 PM 1B: Manufacturing I (Continued) Moderator: Michelle Lam, IBM 1A.4 Physical Insights into the ESD Behaviour of Drain Extended FinFETs B. Sampath Kumar, Milova Paul, Mayank Shrivastava, Indian Institute of Science; Harald Gossner, Intel Deutschland GmbH In this paper, physical insights of Drain extended FinFET under ESD stress condition are explored. Key features like bipolar triggering, conductivity modulation and localized hot spot formation pertaining to DeFinFET failure mechanism are discussed comprehensively. For the first time, catastrophic non-uniform conduction in multi-fingered structure under TLP stress is discussed. 1A.5 Unexpected Latchup Risk Observed in FDSOI Technology Analysis and Prevention Techniques Radhakrishnan Sithanandam, Chanhee Jeon, Kitae Lee, Woojin Seo, Kwanjae Song, Yiseul Kim, Jordan Davis, Dong Yup lee, Sukjin Kim, Hangu Kim, Samsung Electronics FDSOI technology is a low cost, low leakage and high performance planar CMOS technology targeted for the Internet of Things (IOT) and automobile applications. The major differentiating factor of this technology is its ability to dynamically modify the threshold voltage (VT) of the transistors/blocks according to the PPA requirements. This modulation is achieved through biasing the back gate potential located below the buried oxide. This paper reports an un-expected latch-up scenario happened when the FBB/RBB techniques are engineered to its maximum. Through well calibrated TCAD simulations, this latch-up risk is identified and various prevention methods like effect of guard ring parameters, DNW-n-well distance and series resistor are explored and design guidelines are suggested. 1B.4 The Risks of Electric Fields for ESD Sensitive Devices Wolfgang Stadler, Josef Niemesheim, Intel Deutschland GmbH; Stefan Seidl, Reinhold Gaertner, Infineon Technologies AG; Toni Viheriäkoski, Cascade Metrology Oy For objects with different sizes, distances and orientations to an electric field, potentials, charging, and discharge currents of the objects are measured in order to assess the ESD risk due to the E-field. The current rules in ANSI/ESD S20.20 and IEC might need an update to cover worst-case scenarios. 1B.5 ANSI/ESD S20.20 The Next Generation Kevin S. Duncan, Seagate Technology; Ronald J. Gibson, Advanced Static Control Consulting; John T. Kinnear Jr., IBM Corporation As IC technologies evolve in favor of faster IO speeds and increased package sizes, challenging constraints will be placed on future development of on chip ESD protection. Using ANSI/ ESD S20.20 as a baseline, this paper will outline critical elements that factories of the future must consider to be successful. 23

24 Technical Sessions: Tuesday, September 25, Parallel Sessions Exhibitor Showcase: 1:25 PM-1:35 PM HPPI - Booth 209 Session 2A: 1:35 PM-2:50 PM 2A: System Level ESD 1 Moderator: Nate Peachy, Qorvo Exhibitor Showcase: 1:25 PM-1:35 PM Silicon Frontline - Booth 604 Session 2B: 1:35 PM-2:50 PM 2B: RF & High Voltage & MEMS 1 Moderator: Leonardo Di Biccari, STMicroelectronics Invited EMC Paper: 2A.1 Human Body Impedance Modelling for ESD Simulations I. Oganezova, R. Jobava, EMCoS Ltd., Tbilisi State University; D. Pommerenke, J. Zhou, K. Ghosh, A. Hosseinbeig, Missouri University of Science and Technology; J. Lee, Samsung Electronics; N. Tsitskishvili, T. Jobava, Z. Sukhiashvili, EMCoS Ltd. Motivated by understanding the ESD-induced currents from body-worn, wire and hose connected medical equipment is exposed to, a computer simulation is presented to estimate the impedance of a human body relative to ground. This 3D model is the basis for transient field calculation. A method of moments (MoM) frequency domain solution is transformed into time domain via IFFT for further circuit level time domain simulations. The human body is modeled as a homogeneous dielectric with frequency-dependent complex permittivity. Dependence of the impedance on the position of discharge and posture of the human body is investigated. The simulation results are compared with measurements and demonstrate capturing of general tendencies of measured curves. 2A.2 A Proto-type ESD Generator for System Immunity Test of Wearable Devices Junsik Park, Jingook Kim, Samsung Electronics; Jongsung Lee, Cheolgu Jo, Byongsu Seol, Jingook Kim, Ulsan National Institute A proto-type ESD generator for system immunity test of wearable devices is proposed. A wearable device is charged up to an ESD test voltage together with the designed ESD generator and discharged to the ESD current target. The proposed ESD generator for wearable devices is validated with a real ESD measurement. 2A.3An Application System Level Efficient ESD Design for High Speed USB3.x Interface Pengyu Wei, Giorgi Maghlakelidze, David Pommerenke, Missouri S&T; Harald Gossner, Intel Deutschland GmbH A high speed USB3.x IO is analyzed using the System level efficient ESD design methodology using on board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation. 2B.1 Study of Voltage Overshooting of Gate-Coupled Silicon Controlled Rectifier on HBM Protection Zhong Chen, University of Arkansas; Rajkumar Sankaralingam, Gianluca Boselli, Texas Instruments Case study on HBM ESD protection using gate-coupled SCR is presented. The failure mechanism of DENMOS devices due to the voltage overshooting of SCR is discussed. It is demonstrated that effective HBM protection cannot be estimated by only comparing the TLP triggering voltage of gate-coupled SCR and internal circuitry. Additional protection scheme need to be implemented to provide sufficient HBM ESD protection. 2B.2 Design Optimization of a Breakdown Silicon Controlled Rectifier (BDSCR) for Cell Phone Antenna Switch Pin Electrostatic Discharge (ESD) Protection Lin Lin, Robert Gauthier, Alain Loiseau, Xiangxiang Lu, GLOBALFOUNDRIES A new Break-Down Silicon-Controlled-Rectifier (BDSCR) developed for effective ESD protection on antenna ports in cell phone applications is presented in an 180nm silicon-on-insulator (SOI) technology. The new OPPC-BDSCR design achieved leakage, breakdown voltage scaling and ESD requirements. 2B.3 ESD System Level Simulation of MEMS Sensor Modules Gernot Langguth, Friedrich zur Nieden, Claudia Kupfer, Olaf Roesch, Benno Muehlbacher, Elmar Bach, Infineon Technologies System level simulation approach is presented for MEMS sensor modules. Module protection and tester parasitics are modelled as ideal RLC network. On-chip ESD protection simulation is based on compact models. Simulation results can quantitatively explain qualification fails and validate the approach, enabling a subsequent optimization of the overall ESD protection. 24

25 Technical Sessions: Tuesday, September 25, Parallel Sessions Hands-on Session I 1:25 PM-2:45 PM Manufacturing Track Process Assessment Measurements Dale Parkin, Seagate Technology; Wolfgang Stadler, Intel Deutschland GmbH In this hands-on session you will have the possibility to learn, to know, to understand, and to perform measurement methods and approaches for a successful ESD process assessment. ESD process assessment covers risks by charged personnel, ungrounded conductors, and charged device damage. Measurements of grounding, static fields, charges, electrostatic voltages, discharge events and currents are presented and discussed. Use the opportunity to learn from and discuss with leading experts, members of the ESDA Working Group 17 Process Assessment and members of other ESDA standardization groups best practices and advanced measurement methods used for a successful ESD process assessment. Invited Speaker Session: 3:25 PM-4:45 PM I: ESD in Health Care 3:25 PM-4:05 PM Mehdi Kohani, Center for Advanced Life Cycle Engineering (CALCE) ESD is a critical reliability concern for wearable medical devices. Numerous reports of device malfunction resulting in patient adverse events, and medical device recalls have been attributed to ESD. To mitigate the risk of device malfunction that can lead to patient injury or death, sufficient ESD immunity standards and accurate ESD risk prediction models are necessary. The U.S. Food and Drug Administration (FDA) recommends medical device manufacturers to qualify the electromagnetic compatibility of their products according to the IEC collateral standard, within which the IEC standard is the recommended ESD immunity test method. The goal of the present study is to evaluate the effectiveness of the IEC test method for ESD immunity of wearable devices, by designing a series of experiments that represent realistic ESD events. This study also proposes an improved ESD current prediction model for realistic discharge events of wearable devices that involve spark generation. This proposed model is intended to improve the Rompe-Weizel s spark resistance model for ESD current prediction by including additional impedance terms (i.e., capacitive and inductive effects). II: How to Achieve Return on Investment in ESD Control 4:05 PM-4:45 PM Jeremy Smallwood, Electrostatic Solutions ESD control should be an investment achieving adequate return. Implementing standard ESD control is a good starting point but only addresses standard ESD sources. Further improvement requires greater expertise and evaluation of real ESD control needs, and trade-offs between ESD control program variation, equipment, documentation, training and compliance verification costs. INCLUDED with symposium registration 25

26 Technical Sessions: Tuesday, September 25, Parallel Sessions Exhbitor Showcase 3:20 PM-3:30 PM Exhbitor Showcase 3:20 PM-3:30 PM Premix Oy - Booth 609 ESDEMC - Booth 510 Session 3A: 3:30 PM-4:45 PM 3A: System Level Modelling Moderator: Shih-Hung Chen, imec 3A.1 System-Level ESD Simulation in SPICE: A Holistic Approach Yuanzhong(Paul) Zhou, Jean-Jacques Hajjar, Srivatsan Parthasary, Dave Clarke, Brian Moane, Analog Devices Compliance to system-level ESD robustness at the product level is increasingly becoming a competitive advantage. Predicting the classification test level of a design prior to fabrication is critical in achieving first pass success and also addressing key concerns in this regard. Compact models and simulation platform have been developed to predict system-level ESD robustness. 3A.2 Enhanced IC Modeling Methodology for System-Level ESD Simulation Jie Xiong, Maxim Raginsky, Elyse Rosenbaum, Zaichen Chen, University of Illinois Urbana-Champagne; Yang Xiu, Texas Instruments; Zhen Mu, Cadence To enable accurate system-level ESD simulation, power delivery network (PDN) aware quasi-static I-V models are constructed through kernel regression, and recurrent neural networks (RNNs) are used to generate transient models that capture non-quasi-static behaviors of the circuit. Also, a hybrid simulation method including an improved gun model is demonstrated for noise coupling analysis. 3A.3 Predicting System Level ESD Robustness Using a Comprehensive Modelling Approach Christian Russ, Kai Esmark, Infineon Technology; Michael Ammer, Infineon Technologies, Federal Armed Forces Munich The system level ESD robustness of ICs is simulated including all external components. An electro-thermal model is calibrated to power profiles of IC failures. Results provide great confidence for prediction of the joint effectiveness of board- or chip-level protection in reaction to changing system requirements or to different ESD guns. Session 3B: 3:30 PM-4:45 PM 3B: RF & High Voltage & MEMS 2 Moderator: Dolphin Abessolo Bidzo, NXP Semiconductors 3B.1 Trap Assisted Stress Induced ESD Reliability of GaN Schottky Diodes Bhawani Shankar, Rahul Singh, Rudrarup Sengupta, Heena Khand, Ankit Soni, Sayak Dutta Gupta, Srinivasan Raghavan, Mayank Shrivastava, Indian Institute of Science Electro-thermal behavior and degradation of recessed GaN Schottky diode are studied under forward and reverse ESD stress. Impact of different surface treatments at Schottky interface on trap generation and degradation is investigated. Evolution of mechanical stress and defects is probed using on-the-fly Raman spectroscopy. Distinct failure modes are discovered in each case. 3B.2 Study on Latchup Path Between HV-LDMOS and LV- CMOS in a 0.16-μm 30-V/1.8-V BCD Technology Chia-Tsen Dai, Chiao-Tung University, Amazing Mircorelectronic; Ming-Dou Ker, Chiao-Tung University; Yeh-Ning Jou, Shao-Chang Huang, Geeng-Lih Lin, Jian-Hsing Lee, Vanguard International Semiconductor Corp. The latch-up path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30V/1.8V bipolar-cmos-dmos (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latch-up state during the current-trigger latch-up test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latch-up issue. 3B.3 Substrate Isolation Options Effect on HV Latch-up David Marreiro, Vladislav Vashchenko, Maxim Integrated The novel wafer-level test method is applied to determine regularities of HV latch-up dependence upon conventional process technology features. HV latch-up sensitivity is compared for two most common power analog processes - Extended CMOS and BCD. High- and low- side latch-up dependence upon injector-victim spacing is analyzed for useful regularities. 26

27 Technical Sessions: Wednesday, September 26 Year in Review: EOS the Real Challenge or End Of Story (of Communication)? Reinhold Gaertner, Infineon Technologies Wednesday 8:00 AM - 8:40 AM Electrical overstress (EOS) like damages represent a significant percentage of components returned by the customers to the semiconductor manufacturers for comprehensive failure analysis. Typically expectation is that the failure analysis engineer can determine the root cause for the damage (including damaging waveform) just by looking at the failure picture. But this is generally not possible. One of problems with EOS like damages is that different people had a different understandings when talking about EOS-like issues, since there was no definition for a common language. Some time ago the Industry Council for ESD target values published a White Paper on EOS with new definitions for EOS based on absolute maximum ratings (AMR) and they introduced a new terminology called EIPD (electrically induced physical damage) to avoid that EOS is used before there is a clear hint to the root cause. They also introduced a fishbone diagram with specific branches for root causes as a guideline for users to perform a fault tree analysis. This work was picked up by the automotive industry where USCAR and the ESDA published a first document on information exchange needed to be able to find the root cause for possible EOS damages (WG27). Based on this new guideline a two level support will be introduced based on an information sharing between the OEM, tier1 and semiconductor manufacturers that can lead to a higher chance to identify the root cause of the damage and allows to focus on the important topics. Another working group of the ESDA is working on methods to assess and reduce possible EOS problems in production. Exhbitor Showcase 8:50 AM-9:00 AM Magwel - Booth 110 Session 4A: 9:00 AM-10:40 AM 4A: System Level Soft Failures Moderator: Benjamin Orr, Intel Invited ESD German Forum Paper: 4A.1 The Latent Failure Issue Seen from the Other Side: Normal Operation after ESD Induced Degeneration of Devices and Systems Gerhard Groos, Universitaet der Bundeswehr Muenchen; Dennis Helmut, Universitaet der Bundeswehr Muenchen, Technical University of Munich; Gerhard Wachutka, Technical University of Munich This work shows that Transmission-Line-Pulsing method can induce damage to electronic devices without causing a complete malfunction. Yet, this damage can later lead to dysfunction during operation. This could be verified in SMD ceramic capacitors and a CAN bus Transceiver IC. After the TLP stress, a functionality test showed that the device was harmed but not destroyed. Therefore, these defects are inconspicuous within a system, thus latent. Further stress in the allowed operating range (AMR) lead to a gradually deteriorated functionality until the device failed. In the field, the resulted defect would probably be categorized as electrical overstress (EOS) with an unknown root cause. 4A.2 Pin Specific ESD Soft Failure Characterization Using a Fully Automated Set-Up Giorgi Maglakelidze, Pengyu Wei, David Pommerenke, Missouri University; Wei Huang, ESDEMC Technology; Harald Gossner, Intel Deutschland GmbH A fully automated system was developed for the systematic characterization of soft failure robustness in a DUT. The methodology was applied to the USB3 interface and is founded on software-based detection methods, but is also extendable to other interfaces and measurement-based failure detection methods. Exhbitor Showcase 8:50 AM-9:00 AM Simco Ion - Booth 410 Session 4B: 9:00 AM-11:05 AM 4B: Manufacturing ll Moderator: Wolfgang Stadler, Intel Deutschland GmbH 4B.1 Grounding Considerations for RFIC Automated Handling Equipment Testing L.H. Koh, Y.H. Goh, Everfeed Technology Pte Ltd This paper describes the grounding cables selection process in mitigation random degradation of more than 200 automated tester handlers parasitic test yield in a back-end semiconductor factory, testing Radio Frequency Integrated Circuit ESD Sensitive devices, due to stochastic high frequency ground current noise issues. 4B.2 ESD Risks of Containers Made of Conductive Compounds Toni Viheriäkoski, Cascade Metrology; Eira Kärjä, Premix Oy; Pekka Horsma-aho, Treston Oy; Reinhold Gaertner, Infineon Technologies AG; Jeremy Smallwood, Electrostatic Solutions Ltd ESD risk scenarios of conductive containers were assessed by using a system level test generator and different configurations of discharge electrodes. Energy coupling inside the container can be minimized by an applicable mechanical design. Avoidance of the direct or capacitive drain and return path mitigates energy coupling and reduces ESD risks efficiently. 4B.3 Comparison of Surface and Volume Resistance Measurements Made With Various Electrodes Jeremy Smallwood, Electrostatic Solutions Ltd Surface and volume resistance measurements made with standard electrodes are compared with various non-standard electrodes. 27

28 Technical Sessions: Wednesday, September 26 Session 4A: 9:00 AM-10:40 AM (continued) 4A: System Level Soft Failures Moderator: Benjamin Orr, Intel Session 4B: 9:00 AM-11:05 AM (continued) 4B: Manufacturing ll Moderator: Wolfgang Stadler, Intel Deutschland GmbH 4A.3 Measurement and Analysis of System-level ESD-induced Soft Failures of a Sense Amplifier Flip-Flop with Pseudo Differential Inputs Myeongjo Jeong, Junsik Park, Jingook Kim, Uldan National Institute; Jinwoo Kim, Manho Seung, Seokkiu Lee, SK Hynix Inc A sense amplifier flip-flop, which is commonly used as an input receiver in a DRAM, is designed in the simplified motherboard and DIMM structures of a laptop PC. System-level ESD-induced soft failures of the sense amplifier flip-flop are measured and validated with SPICE simulation. 4A.4 Hardware and Software Combined Detection of System-Level ESD-Induced Soft Failures Sandeep Vora, Rui Jiang, Prajwal Mysore-Vijayaraj, Keven Feng, Yang Xiu, Shobha Vasudevan, Elyse Rosenbaum, University of Illinois Urbana-Champagne A semi-custom microcontroller, including a scan chain and voltage monitors, is used to identify which hardware blocks experience soft failures and correlate the occurrence of those failures with the magnitude of noise at inputs and on power supplies. IEC ESD is used to create the soft failure events. 4B.4 EOS/ESD in IC Manufacturing Process of GQFN 64L Devices Bernard Chin, UTAC Headquarters Pte Ltd; L.H. Koh, Everfeed Technology Pte Ltd This paper presents a case study of ESD/EOS events causing low yield in trial lots prior to the release of volume production. The use of line ESD audits to check for static charge, grounding and CDM events, voltage spike check and split lot testing were used to determine the root cause. 4B.5 An ESD Case Study of Defect Analysis in High Speed Electronics Manufacturing Christopher Almeras, Raytheon Integrated Defense Systems A high volume, high speed manufacturer experienced component defects at a rate of 1 in every 30 boards. Failure signature was CDM like. Root cause evaluation was undertaken to find the culprit/s and implement corrective actions. Details of the problem, investigation and corrective action are discussed in this paper. 28

29 Technical Sessions: Wednesday, September 26 1:00 PM 1:30 PM Welcome to the IoT Workshop Harald Gossner, Intel Deutschland GmbH INCLUDED with symposium registration Today s electronic industry is challenged by the needs of ubiquitous Internet of Things penetrating into all realms of society, business and personal life. The basic functional building blocks of IoT devices are sensing, computing and connecting. There is a plethora of IC solutions for each of these features available and their performance is continuously growing. The driving factors for new applications are flexible integration of multiple functions like sensors, microcontrollers or wireless modem devices and the use of highest performance ICs, but at low cost due to the economical scaling effect of high volume products. To fully exploit this for IoT applications, a single IC solution should be scaled into many applications ranging, for example, from industrial to consumer. However, there is a limitation; IoT modules need to comply with very different reliability and robustness requirements depending on the application and the environment. Since the reusing of IC hardware for diverse applications in the fragmented IoT market is a critical factor for market success, adequate design solutions and development strategies for robustness as well as testing and qualification standards are crucial. This workshop brings together experts and industry leaders with strong engagement in IoT who are concerned about the robustness of IoT devices. As this is the first of a kind workshop the focus is on sharing of requirements of various application fields and discussion of the need of new approaches and standards beyond what is already existing. Session A 1:30 PM 5:00 PM Session A IoT Applications A1: IoT Technologies for the Developing Countries: Opportunities & Challenges 1:30 PM-2:15 PM Ramgopal Rao, Indian Institute of Technology Delhi IoT based sensor networks are expected to see a massive growth the world over in the next few years. However, the poor infrastructure facilities available in many of the developing countries and the extreme low cost requirements these technologies are expected to meet pose challenges for an increased penetration of these technologies in such environments. Often times, the social, cultural and the educational background of end users pose a serious challenge for such technology deployment. On the other hand, IoT sensor networks for security, healthcare, agriculture, pedagogy and environment can help improve the quality of life in these societies in addition to providing a secure environment. In this talk, we will discuss some of these challenges and opportunities for development of IoT sensor networks for resource constrained environments based on the experience of the speaker and his group, who have developed and deployed such technologies in the rural areas of India. A2: Cognitive Control of Building HVAC Systems -- Challenges and Lessons Learned 2:15 PM-3:00 PM Steven Hurley, IBM In real-world IoT applications, edge devices should be able handle loss of communication to and receipt of potentially harmful directives from cloud-based systems. We found this to be especially true when developing an IoT-based control system for commercial HVAC systems where room conditions must be maintained despite unreliable upstream connections. In this presentation, I will overview our approach to designing a low-level control device for HVAC systems that replaces traditional PID control loops. In particular, I will discuss the challenges and lessons learned designing an IoT control device that is at least as robust as the PID technology it is designed to replace. A3: IoT Challenges Through Three Examples 3:15 PM-4:00 PM Ramin Poorfard, Silabs The IoT devices are spreading rapidly around the world and the name IoT is becoming almost a house-hold name. Nevertheless, due to the general nature of IoT, its definition and description is often vague and unclear. In this talk, we will use three examples of IoT devices to showcase some of their commonalities and yet highlight their significant differences. In each case, we will describe the IoT system and highlight their particular challenges and reliability considerations. A4: If You Lower Your Shields - System Level Implications of Losing Layers of Surge Protection in Safety-critical IoT 4:00 PM-4:45 PM Michael Paulitsch, Intel Safety critical IoT are on the forefront to be extended with more electronics. Reasons are manifold, like extension of smart diagnosis capabilities, automatic update services, new system-level services due to smart electronics. As a consequence of increased capabilities also mean putting electronics into often harsh environments with potential implications to essential services. The intention of this talk is to discuss some of the potential threats to electronics and compare them to existing and evolving threats. The talk addresses system-level implications and some approaches of shields on system level to protect electronics from harsh environment. It shall also systematically discuss the effects and consequences in safety-critical systems, such as avionics or railway signaling systems as a stimulator for discussions. 29

30 Technical Sessions: Wednesday, September 26, Parallel Sessions Exhbitor Showcase 1:15 PM-1:25 PM IC Data-Advanced Topics Committee Hands-on Session Il 1:25 PM-3:25PM Manufacturing Track II.A ESD Body Walking Voltage Measurement Demonstration 1:25 PM-1:35 PM Ron Gibson, Advanced Static Control Consulting; Dale Parkin, Seagate Technology When a footwear-flooring system is used as the primary ground for personnel that handle unprotected ESD sensitive devices a system resistance and a walking test must be performed. This testing must be completed when qualifying the flooring and footwear for possible use. This tutorial will address the walking test as described in ANSI/ESD STM97.2 along some possible future improvements. II.B Hand Tools and Soldering Irons Qualification and Compliance Verification 1:35 PM-1:45 PM Kurt Edwards, Lubrizol Conductive Polymers WG13 Manufacturing Track Demonstration Abstract: WG13 will demonstrate Soldering/Desoldering test methods from ANSI/ESD S for measuring current leakage, tip to ground reference point resistance and tip voltage. Additionally a demonstration of measurement of resistance tip of hand tool to handle of tool only and tool in system methods. These are a demonstration of testing methods for measurement of resistance of hand tools tip to handle for characterization of the resistance of a hand tool. These demonstrations are to provide examples of test methods to start the evaluation of hand tools for use in EPAs. II.A, II.B Demo Session 1:45 PM-2:25 PM II.C Ionizer Compliance Verification Process 2:25 PM-2:35 PM Matt Strickland, L3 Technologies; Chuck McClain, Northwest Electrostatic Services When ionization is used in the electronics manufacturing process as a static charge control method, it is important to understand the ionization process, and to be able to verify that the control method is effective. Through a short discussion and demonstration, session will provide the attendee with the following useful information: A basic understanding of the theory of ionization The key elements to consider when selecting the ionization method A demonstration of the TR53 ionization compliance verification procedure Provide an opportunity for the attendee to perform the measurements II.D Package Characterization 2:35 PM-2:45 PM Ron Gibson, Advanced Static Control Consulting; Dale Parkin, Seagate Technology Packaging plays a very important role in a complete ESD control program. This tutorial will cover the steps required to qualify packaging materials including the discharge shielding test ANSI/ESD STM which will be demonstrated. II.C, II.D Demo Session 2:45 PM-3:25 PM INCLUDED with symposium registration 30

31 Technical Sessions: Wednesday, September 26, Parallel Sessions Session 6A: 1:25 PM-3:15 PM Session 5A: 1:35 PM-2:25 PM 6A: Testing 5A: System Level ESD 2 Moderator: Nathan Jack, Intel Moderator: Guido Notermans, Nexperia 6A Poster: A Turnkey Method for Calculating Coaxial Cable Loss Effects on CDM Waveforms Timothy J. Maloney, CAI A time domain filter function for the ~2 meters of coaxial cable used for CDM tester waveforms is formulated from online db/m vs. frequency data. Cable losses from dielectric and skin effect losses are incorporated and applied to CDM waveforms. Effects on Ipeak are computed and compared for various cables. 6A.1 Comparison of CDM and CC-TLP Robustness for an Ultra-High-Speed Interface IC Johannes Weber, Heinrich Wolf, Horst Gieser, Linus Maurer, Fraunhofer EMFT; Rita Fung, Richard Wong, Cisco Systems The study compares the CDM and capacitively coupled transmission line pulsing (CC-TLP) robustness of an ultrahigh-speed IC by applying different stress conditions and the influence on current signatures and failure thresholds. It tries to identify the critical stress parameters. Both, flexibility and stability of the CC-TLP characterization method are demonstrated. 6A.2 A New CDM Discharge Head for Increased Repeatability and Testing Small Pitch Packages Evan Grund, Roger Watkins, Grund Technical; Thomas Chang, Bill Reynolds, Chad Burke, Robert Gauthier, GLOBAL- FOUNDRIES The trend toward lower charged device model protection voltage levels as a result of continue device scaling in the semiconductor industry is driving the need for better controlled testing apparatus. A new discharge head design aiming to reduce the signal variations by controlling environmental variables is described in this paper. Invited RCJ Paper: 5A.1 Low Clamping Voltage Protection for Improvement of Powered ESD Robustness Koki Narita, Mototsugu Okushima, Renesas Electronics Corporation An on-chip protection for improvements of powered ESD robustness is presented. The proposed power clamp achieved to reduce the clamping voltage against powered ESD events compared to a conventional RC-triggered clamp by the extending of the big-mos active time with also consideration to false activation. 5A.2 The HMM-TLP Miscorrelation at Wafer Level Tests Vladislav Vashchenko, David Marreiro, Slavica Malobabic, Maxim Integrated; Hossein Sarbishaei, Andrei Shibkov, Angstrom Design Automation A strong miscorrelation between TLP maximum current to failure and corresponding estimated on-wafer-hmm pulse passing level of dual-direction SCR ESD device was studied. For multiple SCR ESD devices in 5-80 V voltage range the effect was represented by low HMM passing level due to burnout of the structure N-pocket to P-substrate isolation junction. It is shown that the phenomenon is specific to the on-wafer HMM test setup itself and is the result of the direct strong coupling of the wafer to the prober chuck at system ground under inductive impedance of the HMM tool connection to the DUT. Session 5B: 2:25 PM-3:15 PM 5B: EOS/ESD EDA Tools Moderator: Efraim Aharoni, Tower Semiconductor, Inc. 6A.3 Undesired Effects of CDM Stressing Non-Connected Pins Theo Smedes, Bob Knoppers, Richard Derikx, NXP Semiconductors; Artemio Garcia, Greg O Sullivan, Micron Technology We show that CDM testing of non-connected pins can result in over-stress or under-stress on the subsequently connected pin tested, and thus can lead to incorrect qualification. Mitigation options are discussed. We show that in particular cases CDM stressing non-connected pins may identify unique fail modes. 6A.4 Device Failure from the Initial Current Step of a CDM Discharge David Johnsson, Krzysztof Domanski, Harald Gossner; Intel Deutschland GmbH CDM discharges exhibit a fast-initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CCTLP methodologies can be addressed by applying pulses with 20 ps rise time. 5B.1 A Design Methodology to Achieve an Area Optimized Power ESD Protection Concept for a Flip Chip Package Nitesh J Trivedi, Harald Gossner, Karthik Ranganathan, Intel Technologies Achieving an optimum power ESD protection is increasingly demanding given the large number of power domains. Flip chip Packages where bumps are placed all over chip allow a larger degree of freedom for area and leakage optimization. A systematic and methodological CAD tool-based approach, to achieve an optimum solution, is presented in this paper. 5B.2 A Study of HBM and CDM Layout Simulations Tools Dolphin Abessolo-Bidzo, Richard Derikx, Paul Cappon, Shuang Zhao, NXP Semiconductors The use of EDA check tools has grown considerably in the past few years in the semiconductor industry. This paper gives an overview of four different HBM and CDM layout simulation tools. A full CDM analysis combining predictive SPICE 31 and layout simulations, is presented for the first time.

32 Technical Sessions: Wednesday, September 26, Parallel Sessions Tutorial Session I: 3:40 PM -5:25 PM Manufacturing Track I.A Meet ESD TR Terry Welsher, Dangelmayer Associates Session 7A: 3:45 PM-5:25 PM 7A: ESD Transient Analysis Moderator: Mariano Dissegna, Texas Instruments Electrical Overstress (EOS) is a term that describes a situation where a device experiences an electrical stress that is greater than one of its expected absolute maximum ratings. In general, any over-voltage, over-current, over-power where the electrical parameter exceeds the specified limits of the device can cause an electrical failure. The focus of this Technical Report is the group of EOS root causes that can cause device damage in manufacturing and test. It is anticipated that this document will be updated frequently as additional information on the many root causes of EOS becomes available. Because of the current availability of detailed information on EMI sources and IC and board-level test these are described in greater detail. The document will be revised as best practices in use in the industry are shared and evaluated by the working group. I.B Changes in ESD/EOS Manufacturing and Control Standards Wolfgang Stadler, Intel Deutschland GmbH; Dale Parkin, Kevin Duncan, Seagate Technology; Brett Carn, Intel The ESDA has currently more than 20 active EOS/ESD manufacturing and EOS/ESD control Working Groups. The Working Groups are continuously creating, updating, revising, and reaffirming documents in the field of ESD and EOS control; approximately 30 EOS/ESD control documents are in process every year. The Short Tutorial will give a brief overview of the most important changes of EOS/ESD manufacturing and control standards in the last years, the current work of the WGs, and what can be expect within the next 1 3 years. I.C Troubleshooting of ESD Issue in Manufacturing Floor Rita Fung, Cisco Systems Electrostatic discharge (ESD) is often one of the top issues to handle at Contract Manufacturer (CM), also known as Electronics Manufacturing Services (EMS). Even though they are certified to ANSI/ESD S20.20 or IEC standards, ESD occurrence is supposed to be lowered, but it still occurs to cause components to damage. High component failure rate at manufacturing severely affecting production throughput becomes a pain point for engineers. Contract Manufacturer, Component Supplier and System Design Company are each playing a key role to troubleshoot the issue. Detailed investigation on factory floor and failure analysis (FA) on component level shall be conducted in parallel. This Short Tutorial introduces a generic 5-step approach with real case examples to root cause the suspected ESD problem in manufacturing environment. 7A.1 Analysis of Forward Recovery in GGNMOS Devices Under Fast Transients Gabriel-Dumitru Cretu, Filippo Magrini, Friedrich zur Nieden, Kai Esmark, Infineon Technologies A GGNMOS device is presented as a vehicle to compare different methods of analyzing the device behavior under fast transient events (CDM, CCTLP, VF-TLP, TCAD mixed mode simulations). The rise-time developed as a key parameter for the failure mode. The necessity, along with the advantages and disadvantages of these methods are discussed. 7A.2 Modelling Transient Voltage Overshoot of a Forward Biased PN-Junction Diode with Intrinsic Doped Region Steffen Holland, Guido Notermans, Hans-Martin Ritter, Nexperia Germany GmbH The transient voltage overshoot of forward biased pn-junction diodes is measured by VF-TLP and compared with TCAD simulations. Based on the simulation results a physics-based analytical model is developed which takes the effect of impact ionization into account and exhibits an excellent match with the TCAD simulations and measurement data. 7A.3 CDM Stress Rise Time: Impact on Forward Recovery Effect for HV ESD Protections Leonardo Di Biccari, Andrea Boroni, Lorenzo Cerati, Lucia Zullino, Luca Merlo, Antonio Andreini,STMicroelectonics Maximum current value, strictly related to the IC package, is used for suitable CDM ESD protections sizing at required CDM voltage level. But recovery effects on HV ESD protections also depend on current rise time, another package-dependent parameter in CDM. The impact of current rise time in CDM test is investigated. 7A.4 Modeling Dynamic Overshoot in ESD Protections Guido Notermans, Hans-Martin Ritter, Steffen Holland, Nexperia Germany GmbH; Dionyz Pogany, TU Wien The dynamic voltage overshoot of an ESD protection during triggering is determined by the conductivity modulation in the silicon and inductive overshoot in the metal connectors. The paper describes the characterization and modeling of this phenomenon and shows how to use this result to boost system protection beyond 15 kv. INCLUDED with symposium registration 32

33 Technical Sessions: Thursday, September 27, Parallel Sessions Year in Review: System Level ESD Design Harald Gossner, Intel Deutschland GmbH Thursday 8:00 AM - 8:40 AM System level ESD has attracted an increasing amount of attention of the ESD community over the last 2-3 years. Following the White Papers on System Level ESd and its relation to IC level ESD protection by Industry Council on ESD Target Levels a number of publications have addressed the topic of system level and IC level protection codesign. Also significant progress has been made in the discussion of standard models of IOs and TVS supporting the codesign approach. Case studies have been discussed in literature which for example highlight the importance of ultrafast discharges in some of the system ESD conditions like the secondary discharge. Another important aspect is the system and PCB analysis methodology like EM scanning and the relevance of system level ESD testing in relation to real world events. The Year-in-Review presentation will offer an overview of these topics critically impacting IC and system design. Session 8A: 8:50 AM-10:30 AM 8A: Numerical Modelling Moderator: Steffen Holland, Nexperia Invited CICC Paper: 8A.1 A Generic Formalism to Model ESD Snapback for Robust Circuit Simulation Tianshi Wang, Colin C. McAndrew, University of California Berkeley This paper introduces a way of modelling the abrupt turn-on/off behavior of ESD protection devices using entirely continuous and smooth equations. It presents accurate and robust ESD snapback models that are convenient and flexible to use for various types of ESD protection devices without convergence issues during simulation. 8A.2 Modeling the Transient Behavior of MOS-Transistors during ESD and Disturbance Pulses in a System with a Generic Black Box Approach Michael Ammer, Infineon Technologies, Federal Armed Forces Munich; Andreas Rupp, Yiqun Cao, Infineon Technologies; Martin Sauter, Linus Maurer, Federal Armed Forces Munich On-chip ESD protection in smart power technologies is often done with MOSFETs, either self-protecting or as dedicated ESD-protection. Turned on by intrinsic capacitive coupling they show dynamic channel current as well as special high current effects. A generic approach to model this transient behavior for system ESD simulation is presented. 8A.4 TVS Transient Behavior Characterization and SPICE-Based Behavior Model Pengyu Wei, Giorgi Maghlakelidze, Abhishek Patnaik, David Pommerenke, Missouri University; Harald Gossner, Intel Deutschland GmbH This paper presents a SPICE model of TVS transient behavior. TVS devices under ESD stress do not turn on instantaneously and a transient overshoot can be observed at start-up. The model includes small signal RF behavior, quasi-static VI curve, inductive overshoot, non-inductive overshoot behavior, and snapback trigger delay. 8A.3 Latch-up Model of Non-collinear PNPN Structures Collin Reiman, Elyse Rosenbaum, University of Illinois; Nathan Jack, Intel Corporation A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to 14-nm FinFET test structures. Layout scaling trends for latch-up characteristics, such as holding and trigger voltages, are captured by the model in circuit simulation. TCAD simulation is used to gain physical insight into the behavior of non-collinear PNPN devices. 33

34 Discussion Groups: Thursday, September 27, Parallel Sessions Discussion Group Session: 8:50 AM-10:20 AM Manufacturing Track DG.A: EOS/ESD Control Program Concerns and Solutions Matt Strickland, L3 Technologies INCLUDED with symposium registration DG.B: ESD Best Practices when Handling Explosives and Energetic Components Jay Skolnik, Skolnik Technical Training The EOS/ESD Control Program Manager or Coordinator faces many daily challenges in either implementing or sustaining a robust static control program. For those just starting out many questions routinely arise such as: What elements should I include in my program? How do I know my production floor workstations are properly grounded? What is an acceptable grounding method How do we handle the requirement in S20.20 on isolated conductors? What about automated manufacturing equipment? What resources are available to help me get started or evaluate my program? The purpose of this discussion group is to bring the seasoned ESD program manager/coordinator, those that are just starting out and those that are somewhere in between, together to have an open conversation of some of the daily concerns about ESD compliance, issues they are facing, and discuss proven ideas on how to build and sustain a robust ESD Control Program. This discussion group is dedicated to continuing the new ESD best practices study when handling energetic / explosive components. Topics will include raw explosives, detonators, volatile chemicals & fumes, safety versus reliability, relative humidity constraints, similarities to the S20.20 standard and differences from the S20.20 standard. We will discuss the common practices being used around the world to funnel the ideas to a set of recommendations. Legal aspects will be discussed, as well. DG.C: System Level ESD Simulations Pasi Tamminen, EDR&Medeso Oy Complex high-speed technologies are challenging to protect against ESD as these require careful signal path design and must survive system level ESD requirements. Therefore, simulations have been an essential part to design ESD robust electronic systems. This workshop focuses on system level simulation methods targeting to locate and mitigate ESD risks before hardware prototypes are available. 34

35 Technical Sessions: Thursday, September 27, Parallel Sessions Session B 9:00 AM -12:30 PM IoT Workshop Session B: Design Devices & Modules & Systems INCLUDED with symposium registration B1: Building a Robust and Secured IOT Edge Device with Advanced Semiconductor Technology 9:00 AM-9:45 AM Xiaolin Lu, TI B3: Heterogeneous Integrated Edge Device Design: Pave the Road to Robust IoT System 10:45 AM-11:30 AM GP Li, UCI This talk will cover the key requirements and challenges for building a generic robust and secured IoT edge device such as smart sensor nodes as well as some of the key semiconductor technologies which are key enablers. An example platform of smart sensor node and its sensor-to-cloud infrastructures for distributed computing examples are introduced. Key applications which fully utilize the salient features of the robust and secured IoT edge device will be discussed as well. B2: Improving the System Integration of Future IoT Devices Using Simulations: Design Approaches and Challenges 9:45 AM-10:30 AM Frederico Centola, Google Smart Devices are becoming ubiquitous and their adoption is only destined to increase in the near future. Some of the factors that are slowing the rate of adoption among consumers are reliability, perceived value, security risks and early obsolescence. The reliability and the robustness of these devices is often not aligned with customers expectations. An optimized design can certainly improve reliability, robustness and the perceived value while also decreasing costs. Integrating biometric sensors that can be touched by the users in very close proximity of antennas is not always trivial (e.g. fingerprint and heart rate monitoring sensors). To add further complexity, the IC module level tests may not provide relevant information to the system level designers. This talk will discuss different system integration design approaches that make use of simulations to understand and improve robustness to ESD, desense and mutual interferences. IoT edge devices form the interface between the physical and digital world and will have at least one sensor. The resulting demand for low cost, small footprint, highly integrated sensor modules is expected to grow at over 10% annually. New technologies and approaches to designing, manufacturing, integrating sensors and ensuring reliability will need to be developed in order to deliver on this demand. This presentation describes the nature of IoT applications, and the heterogeneous integrated technology architecture design to enable these applications. The presentation also describes the types of sensing modules to drive IoT applications. Several examples will be presented to illustrate the types of IoT edge systems, as well as reliable technology design to enable these systems. B4: Convergence of Electromagnetic Engineering in Systems 11:30 AM-12:15 PM Ajay Kumar Vaidhyanathan, Intel Signal Integrity, power delivery, Electromagnetic Compatibility, RF and antennas different aspects of electromagnetic engineering. SI typically is onedimensional, Power Integrity is two dimensional and Electromagnetic compatibility is a combination of one, two and three-dimensional simulation problems. The challenge is between SI/PI/EMC/RF optimization which pose conflicting requirements. In most designs the number of PCB layer is driven by cost of BOM and Z-height. Also, some designs like Phones, tablets, dual display have a 3-6 month development cadence. Ideally you have to get the system out in just 1-2 iteration. In this case optimizing design might have to be part data driven and part engineering judgment. Certain areas like SI will have the scope to cover by getting a large set of data using technical methods. PI on the other hand will have just scope to run point simulation. EMC simulation typically needs to done in the background more to give insight during debug. 35

36 Technical Sessions: Thursday, September 27, Parallel Sessions Session 9A: 10:50 AM-12:05 PM 9A: ESD Test Cases Moderator: Robert Gauthier, GLOBALFOUNDRIES 9A.1 Power-Rail ESD Clamp Circuit with Polysilicon Diodes Against False Trigger During Fast Power-ON Events Jie-Ting Chen and Ming-Dou Ker, National Chiao-Tung University A new power-rail ESD clamp circuit with both timing and voltage-level detection mechanisms is proposed against false trigger events. The diode string is used to detect the overstress voltage level during ESD events. By using the polysilicon diode, the standby leakage current along the proposed power-rail ESD clamp can be effectively reduced. 9A.2 ESD and Latch-Up Failures Through Triple-Well in a 65nm CMOS Technology David Alvarez, Wolfgang Hartung, P.R. Bhandari, Infineon Technologies ESD and latch-up failures in a 65 nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances is studied for this type of parasitic device. 9A.3 ESD Study on a-igzo TFT Device Architectures Marko Simicic, Geert Hellings, Shih-Hung Chen, Kris Myny, Dimitri Linten, imec The thin-film-transistor (TFT) indium-gallium-zinc-oxide (IGZO) technology offers to manufacture transistors on large and flexible substrates at low processing temperatures and at a low cost. However, optimization of ESD protection devices in this technology has not been thoroughly investigated. This paper analyzes the ESD performance of three different TFT device architectures. 36

37 Short Tutorial Sessions: Thursday, September 27 Tutorial Session Il: 10:40 AM-12:25 PM INCLUDED with symposium registration Manufacturing Track ll.a Suspect Counterfeit ESD Packaging and Materials have Infiltrated the Commercial & DOD Supply Chain Bob Vermillion, RMV Technology Group LLC Did you know that even though the original components are genuine, the outer protective packaging may be suspect counterfeit or ESD non-compliant? Suspect counterfeit packaging can damage EEE Parts (ESD sensitive devices)? Organizations can no longer rely upon a supplier s Technical Data Sheet as proof of compliance to ANSI/ESD S541 or Mil-Standards. To mitigate the increase of non-compliant or Suspect Counterfeit materials and packaging, due diligence by the user must include Incoming Inspection testing beyond the traditional visual review process. Instrument driven ANSI/ESD S541 testing methods are a first step towards supplier compliance. Today s Incoming Inspection must include the adoption of ANSI/ESD S541 Static Control Packaging Evaluation Methods that house commercial off the shelf (COTs) or government off the shelf components (GOTs). Moreover, the End user cannot assume that a product is protected in an ESD safe protective package such as a grid bag that provides little to no static shielding even though incorporation a printed black grid pattern and an ESD symbol. Many OEMs, Distributors and End Users in both the commercial and DoD Supply Chain have been compromised. In three case histories for suspect counterfeit dip tubes (IC carriers), JEDEC trays and tape & reel packaging, one will see the potential risk that can occur during staging, assembly, transport and pick and place. ll.b Limitations of Test Equipment and Understanding Measurement Results Dave Swenson, Affinity Static Control Consulting, LLC One of the great things about the study of electrostatics is that all the important aspects can be measured. The troublesome aspect of the study of electrostatics is that all the important aspects can be measured. This obvious paradox results from misunderstanding how to apply test methods and then misinterpreting the results. Each of the properties of electrostatics can be measured with instruments available today. Selecting the proper measurement tool is often a matter of understanding the application and having a reasonable idea about what the control material or item of interest is supposed to do. If you misinterpret the application, it is likely that you will not select the correct measurement tool. In this short tutorial, we will review the possible measurements, the instruments that could be used and how the measurements could aid in evaluation of an application. ll.c Common ESD Problems in Manufacturing and Testing Pasi Tamminen, EDR&Medeso Oy ESD Control Programs based on ANSI/ESD S20.20 and IEC standards can provide an efficient environment to minimize ESD risks. The coverage of these programs can vary from mostly image and show, to a more technical oriented approach. However, ESD Control Programs should be built based on the required protection level which depends largely on the type of electrostatic discharge sensitive components (ESDS) and the way ESDS are handled. In a manual handling process a basic control program focusing on personnel groundings and ESD safe materials can prevent more or less all ESD event based failures. However, when the handling processes contain widely different electrical products, mechanical components with dielectrics, and automated processes, some of the possible discharge risk scenarios may not be fully covered. There are also challenges to select and verify that all materials used in electrostatic protective area (EPA) really fulfil set technical requirements. In this presentation we show statistical data of electrical failures collected in electronics manufacturing and some typical ESD and Electromagnetic Interference (EMI) failure cases found in EPAs. The presented failure cases and failure sources represents mainly electronics assembly processes in industrial, commercial, automotive, and medical electronics area. Here a typical electronic product is not a single IC but an subassembly or semi-finished system with highly varying materials and handling steps. In addition, typical prevention, control and detection methods are presented to establish a more comprehensive ESD control protection process. 37

38 Technical Sessions: Thursday, September 27, Parallel Sessions Session C&D: 1:30 PM 3:45 PM IoT Workshop INCLUDED with symposium registration Session C - Handling of IoT System Session D New Standards for Robustness Design and Testing of Modular IoT Systems C1: Is 1kV Also Enough for IoT ESD Protection Do Current Test Methods and Models Apply? 1:30 PM-2:15 PM Koen Verhaege, Sofics D1: How Amazon Builds Robust Consumer and Smart Home Products? 2:15 PM-3:00 PM Guneet Sethi, Amazon Integrated circuits designed for Internet of Things (IoT) applications require special attention with respect to ESD and EOS protection. Because of the form factor the transient voltage suppressors are typically left out while the probability to receive stress increases. In this work we summarize the usefulness of current ESD standards for several IoT case studies. The electronics industry is getting flooded with IoT (Internet of Things)-based consumer and smart home products. The development times for these products are becoming shorter, product life expectancy is continuing to rise and cost pressures continue to persist. In addition, there are no industry standard hardware reliability specifications for consumer and smart home products unlike the semiconductor or automotive industries. Building robust devices that delight consumers is getting challenging due to the above tenants. This workshop will highlight the key principles, tools, and techniques that Amazon uses to build robust consumer and smart home hardware products. It will demonstrate the methodology that the Amazon Lab126 hardware reliability team uses to create reliability specifications focusing on various customer use case scenarios and challenges associated with the methodology. Using the stress-strength approach the reliability specification can be combined with reliability test performance to estimate the field risk associated with the observed failure. Real world examples will be utilized to demonstrate the reliability tools and techniques. D2: ESD Robustness of IoT Devices: Are We Going to Face New Challenges? 3:00 PM-3:45 PM Heinrich Wolf, FhgFraunhofer Research Institution for Microsystems and Solid State Technologies EMFT Panel Discussion 4:00 PM-4:45 PM The Internet of Things (IoT) describes a rapidly growing market. Depending on the application the environmental conditions can be completely different for IoT devices. Furthermore, the growing complexity of these devices increase also the susceptibility related to hardware or software related failures. This presentation will discuss real world examples which required more than the standard qualification tests in order to reveal and fix weaknesses in the design. IoT Workshop Closing 4:45 PM-5:00 PM 38

39 WORKSHOPS: Tuesday, SEPTEMBER 25 Parallel Sessions Session A: 5:05 PM - 6:20 PM A.1 Industry Council s Next Thresholds Targets Do We Need Lower Targets, and Can We Achieve Them? Nathan Jack, Intel Corporation; John Kinnear IBM Corporation Several years ago, the Industry Council on ESD Target Levels released two whitepapers recommending reduced ESD testing thresholds: 1kV for HBM (2007) and 250V for CDM (2009). Nine years later, scaling and performance trends have chipped away at the ESD design window making it difficult for advanced technologies and products to achieve these targets. Has the time come for further reductions to the recommended HBM and/or CDM target levels? Will future products and technology nodes necessitate this decrease? What might the future roadmap timeline look like? What additional factory control measures would be required? The purpose of this workshop is for participants to share the challenges they foresee in achieving the existing targets in the future, as well as the challenges the predict in terms of factory control and customer acceptance. This feedback will be delivered to the Industry Council as they deliberate the future roadmap for recommended threshold targets. A.2 EDA Solutions for ESD System Level Michael Khazhinsky, Silicon Laboratories, Inc.; Matt Hogan, Mentor, A Siemens Business There is a significant gap between component and system level test methods and standards. Increased interest for holistic system level solutions, particularly for automotive and IOT applications have sponsored efforts to close this gap. With revisions being made to various standards, like ISO and AEC-Q100, what considerations are being made for system level compliance? How do we automate and capture necessary parameters to educate those in the field? How well do you know/understand SEED and it s applications? Is there an understanding of board/ic interaction under IEC testing conditions? What are the design strategies and how can they be supported by EDA tools. How does system level information (PCB design, etc.) get passed to EDA tools? How can this information be used by EDA tools to support ESD and EMI compliance qualification of the systems as well as IC components? What additional information and analysis are needed? What are missing EDA tool capabilities? There are lots of questions. Bring your experiences, thoughts and innovations. Things get solved when you get involved. A.3 Latch-up Testing JESD78F and Beyond Marty Johnson, Texas Instruments, Inc; David Eppes, Advanced Micro Devices Latch-up prevention is an aspect of semiconductor design that can be as challenging if not more challenging than ESD to address. Failure to detect a latch-up problem during qualification can be costly to resolve if a customer detects it for you or you (as a customer) detects it for your suppliers. Applying the correct method for latch-up testing is critical for detecting latch-up problems and providing accurate results to customers. Factors such as shrinking and more complex fabrication processes, increasing system complexity, higher-pin counts, use of mixed voltages (some as high as 100 V or greater), and power management combine to create even greater challenges when latch-up testing. This workshop will provide a preview of changes for the upcoming update of the JEDEC JESD78E Latch-Up specification to JESD78F. In addition, the workshop will delve into the following questions: What are the challenges you currently face when testing for Latch-up? What challenges to you foresee in the future? What are the do s and don ts of latchup testing? How can the current latch-up test methodology be improved? Come share your experiences and expertise so that we can address these questions together. A.4 Process Assessment of Automated Handlers Reinhold Gaertner, Infineon Technologies; Arnie Steinman, Electronics Workshop; Jim Roberts, Continental Automotive Recent years have witnessed an increasing use of automation in the electronics industry. There is hardly a device, circuit board, or assembly that does not undergo one or more types of automated handling at some point during its production cycle. With the continuing decrease of ESD withstand voltage for both devices and circuit assemblies, it becomes increasingly important to assure that they can be safely handled by the automated handlers. Responsibility for determining this is ultimately shared by the manufacturers and end users of the equipment. There is no clear industry blueprint as to how this should be done, but work is ongoing. What documents are available describing process assessment methods for handlers? What methods are you using to qualify automated handlers for your or your customers manufacturing process? Share your methods and experiences. 39

40 WORKSHOPS: WEDNESDAY, SEPTEMBER 26 Parallel Sessions Session B: 5:45 PM - 7:00 PM B.1 Can Everyone Agree on what AMR Means? Charvaka Duvvury, ESD Consulting, LLC; Theo Smedes, NXP Semiconductors; Stevan Hunter, ON Semiconductor B.3 Qualification of Packaging Material Use of Packages Outside of an EPA Dave Swenson, Affinity Static Control Consulting, LLC; Dale Parkin, Seagate Technology In the discussion on Electrical Overstress (EOS) the concept of Absolute Maximum Ratings (AMR) plays an essential role. One might think AMR is a simple concept, but it is still not properly understood and remains as a controversial issue. The industry Council White Paper on EOS and the work of the ESDA Working Group 27 (Automotive EOS) use the definition that electrical overstress occurs as soon as a product exceeds its AMR. But what does that mean in practice? How do suppliers determine and specify AMR? How do customers interpret AMR? Are AMR ratings really used during the design phase? How do OEMs assure that their application does not bring components outside its safe region? Questions like these will be addressed and discussed in this highly interactive workshop, that will be conducted in the now well-known world café format. With your help we hope to bring some clarity to this controversial topic. B.2 System Level Testing (CDE, CBE, HMM,) - What Does Industry Really Need? Tom Meuse, Thermo Fisher Scientific; Fabrice Caignet, LAAS-CNRS As more and more embedded electronics are being used in new applications, such as automotive, the pressure to guarantee the robustness of the system level ESD designs is increasing. For equipment manufacturers, it is crucial that their systems can withstand ESD events, in order to guarantee that the embedded electronics will survive in their final application. Papers presented in the recent years have shown that, depending on the system application devices are not exposed to the same stresses. So when we are talking about IEC , is it really the relevant stress since the application changes what the device may see for a stress? Do we have to consider separate applications, domains or interfaces like multimedia (phones, USB3), medical applications, automotive, aeronautics? Is it reasonable to have the same system level tests for all application domains? Can we assess what test is best suited for particular applications? In this Workshop, we hope to identify different system level applications and the appropriate tests requirements for these applications. Different experiences and inputs are important, so please join and provide your insights. ESD Association Standard ANSI/ESD S541 continues to provide information and requirements for the use of packaging materials inside an EPA as well as for storage and transport of products outside of an EPA. Packaging materials used outside of an EPA require the same considerations as the packaging used inside of an EPA with the added requirement of shielding from electrostatic fields and electrostatic discharge. This workshop will provide a forum for the discussion of the requirements for packaging used outside of an EPA. After a brief introduction regarding the requirements stated in S541, the audience will be able to ask questions as well as respond to questions from the moderators. The experience of the attendees should provide valuable insight to the subject of packaging attributes and requirements. B.4 IoT workshop What is Different in Regards to Robustness Requirements in a Connected World of IoT Devices? Harald Gossner, Intel Deutschland GmbH IoT devices are becoming ubiquious and are influencing and controling life literally in any way. This includes safety relevant and ultra high reliability applications. However, connected and high compute intense applications cannot rely on dedicated IC solutions for high robustness due to high cost. Also sensors represent a challenge in terms of high reliabity and life time. The workshop is dedicated to the discussion which dedign approaches and test methods need to be applied to achieve the required robustness on module level. The scope of the workshop extends beyond ESD to EOS as well as life time requirements. 40

41 Exhibit Hall You will find a broad spectrum of products and services for static protection, control, testing, and analysis, as well as prominent trade publications, all in one location for your convenience. Exhibits are open to the public. Exhibit Hours Monday, September 24 Welcome Reception 6:00 p.m. - 9:00 p.m. Tuesday, September 25 9:30 a.m. - 5:30 p.m. Wednesday, September 26 8:30 a.m. - 1:30 p.m. Ten minute showcase presentations from exhibitors are scheduled at the beginning of select technical sessions. A complimentary coffee bar is available in the exhibit hall for all visitors. Tuesday lunch service will be available in the exhibit hall for anyone wishing to purchase lunch while visiting the exhibits. Exhibitor 3DXTECH ACL Staticide, Inc. Advanced Test Equipment Rentals Ansys, Inc. Barth Electronics, Inc. BioFit Engineered Products BootieButler Botron Company, Inc. Clean Control Tech Corp. Conductive Containers, Inc. Core Insight, Inc. Dangelmayer Associates, LLC Desco Industries, Inc. Dou Yee Enterprises (S) Pte. Ltd. Electro-Tech Systems, Inc. EMWorks ESDEMC Technology, LLC ESDMAN Co., Ltd. Essentium Materials, LLC Estatec LLC ESTION Technologies GmbH Flambeau, Inc. GIBO/KODAMA Chairs Grund Technical Solutions, Inc. HANWA Electronic Ind. Co., Ltd. HPPI GmbH In Compliance Magazine Innovative Circuits Engineering it2 Technologies Lubrizol Engineered Polymers Magwel Megalin Source International Co., Ltd. Mentor, A Siemens Business Modern Dispersions, Inc. Monroe Electronics Electrostatic & ESD, an Advanced Energy product line NRD, LLC Phasix ESD Poly Drop, LLC Polyonics Premix Oy Prostat Corporation/Stephen Halperin & Associates Ltd. RTP Company Shenzhen Btree Industrial Co., Ltd. Shoe Inn, LLC Silicon Frontline Technology, Inc. Simco-Ion Statico StaticStop, a division of SelecTech, Inc. Synopsys, Inc. Tech Wear, Inc. Thermo Fisher Scientific Transforming Technologies TREK, an Advanced Energy Company Associations/Publications ASM International Electronics Protection How2Power Interference TechnologyInstitute of Environmental Sciences and Technology Surface Mount Technology Association US Tech Booth number

42 EOS/ESD Association, Inc. Officers President Ginger Hansel, Dangelmayer Associates, LLC, Austin, TX Senior Vice President Alan Righter, Analog Devices, Inc., San Jose, CA Vice President Harald Gossner, Intel Deutschland GmbH, Neubiberg, GERMANY Treasurer John Kinnear Jr., IBM Corporation, Poughkeepsie, NY Secretary Nathaniel Peachey, Qorvo, Inc., Greensboro, NC Past President Gianluca Boselli, Texas Instruments, Inc., Dallas, TX Headquarters Operations Lisa Pimpinella, Executive Director Christina Earl, Standards Senior Program Manager Nicholas Pimpinella, Administrator, Programs Brennan Pimpinella, Administrator, Marketing Chantelle McVey, Administrative Assistant Board of Directors Gianluca Boselli, Texas Instruments, Inc., Dallas, TX Brett Carn, Intel, Hillsboro, OR Lorenzo Cerati, STMicroelectronics, Agrate Brianza, ITALY Cheryl Checketts, Estatec, Mesa, AZ Charvaka Duvvury, ESD Consulting, LLC, Plano,TX Reinhold Gaertner, Infineon Technologies, Neubiberg, GERMANY Robert Gauthier, GLOBALFOUNDRIES, Essex Junction, VT Harald Gossner, Intel Deutschland GmbH, Neubiberg, GERMANY Ginger Hansel, Dangelmayer Associates, LLC, Austin, TX Matthew Hogan, Mentor, A Siemens Business, Wilsonville, OR Michael Khazhinsky, Silicon Laboratories, Inc., Austin, TX John Kinnear Jr., IBM Corporation, Poughkeepsie, NY Junjun Li, IBM Corporation, Poughkeepsie, NY Nathaniel Peachey, Qorvo, Inc., Greensboro, NC Lisa Pimpinella, EOS/ESD Association, Inc., Rome, NY Alan Righter, Analog Devices, Inc., San Jose, CA Mirko Scholz, imec, Leuven, BELGIUM Wolfgang Stadler, Intel Deutschland GmbH, Neubiberg, GERMANY David E. Swenson, Affinity Static Control Consulting, LLC. Scott Ward, Texas Instruments, Inc., Dallas, TX Terry Welsher, Dangelmayer Associates, LLC, Suwanee, GA Joshua Yoo, Core Insight, Inc., Seongnam-City, Gyeonggi-do, SOUTH KOREA Steering Committee General Chair James W. Miller, NXP Semiconductors, Austin, TX Vice General Chair Guido Notermans, Nexperia, Hamburg, GERMANY Tutorial Program Chair Wolfgang Stadler, Intel Deutschland GmbH, Neubiberg, GERMANY Technical Program Chair Lorenzo Cerati, STMicroelectronics, Agrate Brianza, ITALY Workshops Chair Wolfgang Stadler, Intel Deutschland GmbH, Neubiberg, GERMANY Arrangements Chair Cheryl Checketts, Estatec, Mesa, AZ Registration Chair Raivo Leeto, Sandia National Laboratories, Albuquerque, NM Audio/Visual Co-Chair Souvick Mitra, GLOBALFOUNDRIES, Inc., Essex Junction, VT Audio/Visual Co-Chair Ann Concannon, Texas Instruments, Inc., Santa Clara, CA Tutorial Audio/Visual Matt Strickland, L3 Technologies, San Diego, CA Technical Liaison Michael Khazhinsky, Silicon Laboratories, Inc., Austin,TX Information David E. Swenson, Affinity Static Control Consulting, LLC, Austin, TX Past General Chair Junjun Li, IBM Corporation, Poughkeepsie, NY EOS/ESD Association, Inc. Vice President Harald Gossner, Intel Deutschland GmbH, Neubiberg, GERMANY Publications & Marketing HQ Operations, EOS/ESD Association, Inc., Rome, NY Technical Program Committee Technical Program Chair Lorenzo Cerati, STMicroelectronics Adrien Ille Infineon Akram Salman TI Benjamin Orr Intel Benjamin Viale STMicroelectronics Charvaka Duvvury TI Fellow Emeritus Chuck McClain Micron Dale Parkin Seagate David Eppes AMD David Pommerenke MS&T Dimitri Linten imec Dionyz Pogany Vienna University Dolphin Abessolo Bidzo NXP Efraim Aharoni Tower Semiconductor Eleonora Gevinti STMicroelectronics Evan Grund GTS Fabrice Blanc ARM Fabrice Caignet LAAS-CNRS Farzan Farbiz Apple Friedrich Zur Nieden Infineon Gene Worley Qualcomm George Kong Peregrine Semiconductor Gernot Langguth Infineon Gianluca Boselli TI Guido Notermans Nexperia Harald Gossner Intel Hiroyasu Ishizuka Synaptics Jam-Wem Lee TSMC Javier Salcedo Analog Jay Skolnik Skolnik Technical Johannes Weber Fraunhofer Joshua Yoo Core Insight Kai Esmark Infineon Kathy Muhonen Qorvo Kuo-Hsuan Meng NXP Leonardo Di Biccari STMicroelectronics Mariano Dissegna TI Markus Mergens QPX Masanori Sawada HANWA Electronics Matt Strickland L-3 Matthew Hogan Mentor Mayank Shrivastava Indian Institute of Science (IISc) Bangalore Melanie Etherton NXP Michael Khazhinsky Silicon Labs Michael Stockinger NXP Michelle Lam IBM Mike Chaine Micron Mototsugu Okushima Renesas Nate Peachey Qorvo Nathan Jack Intel Nicolas Nolhier LAAS-CNRS Nitesh Trivedi Intel Pasi Tamminen EDR&Medeso Robert Ashton OnSemi Robert Gauthier GlobalFoundries Robert Mertens NXP Shih-Hung Chen imec Souvick Mitra GlobalFoundries Steffen Holland Nexperia Stephen Fairbanks SRF Technologies, LLC Teruo Suzuki SocioNext Theo Smedes NXP Tim Maloney Center for Analytic Insights Toni Viheriäkoski Cascade Metrology Vladislav Vashchenko Maxim Integrated Wolfgang Stadler Intel Yiqun Cao Infineon Zhong Chen University of Arkansas 42

43 Accomodations EOS/ESD Symposium and Exhibits, September 23-28, 2018 The Peppermill Resort and Casino, Reno, NV, USA All reservations must be received by September 6, 2018 Room Rates Room Rate: $ Tax (Resort Fee Waived) *Guests must identify themselves with the group name 2018 EOS/ESD Symposium and Exhibits or code below- to receive the above-mentioned, discounted room rate. To Reserve Your Room: Call In: refer to Group Code- CESDA18 Reservations Link: Name: Company: Address: City: State/Province: Zip/Postal Code: Country: Phone: Accommodations Requested ($130 Single/Double) King Double Number of People Accommodations under the Americans with Disabilities Act Room rates shown do not include applicable taxes and surcharges. Arrival Date: Departure Date: List all persons who will be sharing accommodations UNAUTHORIZED HOUSING Housing block pirates now routinely poach event attendees and exhibitors! Pirating companies gather group s contact information from published or online directories. They call attendees leaving the impression that they are an official housing representative. They will also frequently cite an imminent sell-out of the block while urging you to secure housing immediately. Another tactic is to offer a room rate that is significantly less than the official rate. Offered rooms may be substandard or at other properties. Please do not respond to these solicitations or book your rooms with any housing organizations that claim to represent EOS/ESD Association, Inc. Booking via the hotel link or calling the number we provided are the only safe and reliable methods for booking your hotel reservations. Reservations When reserving your room, in all instances, identify yourself as a participant of the EOS/ESD Symposium. Cancellation of reservation must be made at least seven days prior to arrival date or you will be charged one nights room/tax. Check-in Time is 4:00 p.m. - Check-out Time is 12:00 Noon. Resort Fee: Fee Waived - Services include: WIFI in hotel room, fitness center, self-parking, unlimited local and toll free phone calls, and complimentary shuttle services to local hot spots. 43

44 Registration - page 1 EOS/ESD Symposium and Exhibits, September 23-28, 2018 The Peppermill Resort and Casino, Reno, NV, USA Mr./Mrs./Ms.: First Name: Last Name: Company Name: Job Title: Street: City: State/Province: Country Zip/Postal Code: Address is (please circle the one that applies) Home or Company Phone: Register Online! Please fill out all sections (1 thru 4) of this form. Sections 3 and 4 are on next page. 1 Please Print or Type (Your name and company will appear on badge and/or certificate exactly as written below.) 2 Tutorial Registration Check each session attending, one session per time slot. SUNDAY, SEPTEMBER 23 & MONDAY, SEPTEMBER 24 FC340: 8:00 a.m. - 5:00 p.m ESD Program Development and Assessment (ANSI/ESD S20.20) (PrM) SUNDAY, SEPTEMBER 23 FC100: 8:00 a.m. - 4:30 p.m. ESD Basics for the Program Manager (PrM) DD110: 8:00 a.m. - 12:00 p.m. ESD Basics to Advanced Protection Design (DD) DD200: 8:30 a.m. - 12:00 p.m. Charged Device Model Phenomena, Design, and Modeling (DD) DD/FC130: 8:30 a.m. - 12:00 p.m. System Level ESD/EMI: Testing to IEC & Other Standards (PrM), (DD) FC200: 8:30 a.m. - 12:00 p.m. Packaging Principles for the Program Manager (PrM) FC165: 8:30 a.m. - 12:00 p.m. Novel Methods for Fixing ESD Issues in the Factory for both Electronics & Explosive Products DD201: 1:00 p.m. - 4:30 p.m. ESD Protection and I/O Design DD204: 1:00 p.m. - 4:30 p.m. ESD Design in HV Technologies FC370: 1:00 p.m. - 4:30 p.m. Basics of EMI and EOS in Manufacturing Environment and First Mitigation FC365: 1:00 p.m. - 4:30 p.m. Practical Applications of Ionization NEW DD311: 1:00 p.m. - 4:30 p.m. Impact of Technology Scaling on Components High Current Phenomena and Implications for Robust ESD Design (DD) MONDAY, SEPTEMBER 24 FC101: 8:30 a.m. - 4:30 p.m. How To s of In-Plant ESD Auditing and Evaluation Measurements (PrM) DD231: 8:30 a.m. - 12:00 p.m. ESD System Level: Physics, Testing, Debugging of Soft and Hard Failures DD100: 8:30 a.m. - 12:00 p.m. ESD Circuits FC120: 8:30 a.m. - 12:00 p.m. Air Ionization Issues and Answers for the Program Manager (PrM) DD/FC250: 8:30 a.m. - 12:00 p.m. What Information Needs to be Exchanged for Potential EOS Problem NEW DD115: 8:30 a.m. - 10:00 a.m. Latch-Up Basics and Testing NEW DD117: 10:30 a.m. - 12:00 p.m. TCAD Fundamentals DD300: 1:00 p.m. - 4:30 p.m. Circuit-Level Modeling and Simulation of On-Chip Protection (DD) REVISED DD340: 1:00 p.m. - 4:30 p.m. Integrated ESD Device and Board Level Design FC215: 1:00 p.m. - 4:30 p.m. Device Technology and Failure Analysis Overview (PrM) DD/FC330: 1:00 a.m. - 2:30 p.m. Control of Charged Board Event (CBE) DD317: 1:00 p.m. - 2:30 p.m. ESD Challenges in Advanced FinFET and GAA NW CMOS Technologies FC201: 3:00 p.m. - 4:30 p.m. ESD - A Surprisingly Frequent Root Cause of Device Failure Emerging Topic: 3:00 p.m. - 4:30 p.m. Technology and ESD Challenges Towards 7 nm NEW THURSDAY, SEPTEMBER 27 FC170: 8:30 a.m. - 4:30 p.m. ANSI/ESD S20.20 ESD Program Assessment for Internal Auditors and Supplier Quality Engineers DD260: 8:30 a.m. - 12:00 p.m. Design for EOS Reliability DD150: 8:30 a.m. - 12:00 p.m. Introduction to RF ESD Design NEW FC110: 8:30 a.m. - 12:00 p.m. Cleanroom Considerations for the Program Manager (PrM) FC361: 8:30 a.m. - 12:00 p.m. Ultrasensative (class 0) Devices: ESD Controls and Auditing Measurements REVISED DD/FC165: 8:30 a.m. - 10:00 a.m. Design Engineer - Weak Link or Warrior in the ESD Battle NEW DD213: 10:30 a.m. - 12:00 p.m. ESD, EOS, and Latch-up Failure Analysis for Designers FC262: 1:00 p.m. - 4:30 p.m. Electrical Fields and Particles - Practical Considerations for the Factory FC150: 1:00 p.m. - 4:30 p.m. Hands-on ESD Measurments & Instruments - Uses and Pitfalls FC360: 1:00 p.m. - 4:30 p.m. Electrical Overstress (EOS) in Manufacturing and Test DD220: 1:00 p.m. - 4:30 p.m. Transmission Line Pulse (TLP) Basics and Applications (DD) DD381: 1:00 p.m. - 2:30 p.m. Electronic Design Automation (EDA) Solutions for ESD DD382: 3:00 p.m. - 4:30 p.m. Electronic Design Automation (EDA) Solutions for Latch-up Please continue and fill out all sections (3 and 4) of this form on next page 44

45 Registration - page 2 Register Online! EOS/ESD Symposium and Exhibits, September 23-28, 2018 The Peppermill Resort and Casino, Reno, NV, USA Remember to fill out sections 1 and 2 on page 1 of this form. Please Print or Type First Name: Company Name: Phone: Last Name: 3 Fees: Please check appropiate boxes. Save by registering in advance! This will facilitate your registration upon your arrival at the Symposium. Early registration and member discounts* are valid only if received no later than July 24, Symposium $800 (Includes technical sessions, workshops, and exhibits) Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $600/Non-Members $700 Tutorials $710 (Sunday, Monday, OR Thursday (Full Day)) Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $510/Non-Members $610 Bundled Fees $2,465 (Symposium plus Sun., Mon., and Thurs. full tutorial days) Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $1,765/Non-Members $2,165 ESD Program Development and Assessment (ANSI/ESD S20.20) $1,710 (Attendance limited to first 30 registrants) This seminar is not included in the bundled fee. Early Registration Fees valid until July 24, 2018 EOS/ESD Association, Inc. Members* $1,510/Non-Members $1,610 4 Payment: Company purchase orders not accepted. Check (Make payable to EOS/ESD Association, Inc.) TOTAL ENCLOSED $ Type: Visa Master Card AMEX Discover Credit Card # Expiration Date: Code: Print Name on Card: How did you learn about this event? Under the Americans With Disabilities Act, I require auxiliary aids or services. I am taking the ESD Certified Professional-Program Manager exam: I am taking the ESD Certified Professional-Device Design exam: First Time Attending *Membership discounts apply to those who participate as members all year long and are current at the opening of symposium registration. Memberships processed after this date will not apply. You will receive a complimentary 2019 membership with your Symposium registration which will allow you to enjoy the full benefits of membership in Student Fees The EOS/ESD Association, Inc. offers a fifty percent discount for full-time students. Proof of enrollment required. Student fees apply only to symposium or tutorial registration and do not apply to bundled fees, ANSI/ESD S20.20 seminar, or Emerging Topics. Register 5 or more people from one company at the same time and save $100 per person. Please contact EOS/ESD Association, Inc. prior to registering. Billing Address: City State Zip Include payment with this form. Mail form and payment to: EOS/ESD Association, Inc., 7900 Turin Road, Bldg. 3, Rome, NY , USA, Tel: Students must include proof of full-time enrollment to obtain student fees. Only U.S. currency, checks drawn on a U.S. bank that is a member of the U.S. Federal Reserve, travelers checks payable in U.S. dollars, and credit cards (Visa, Master Card, AMEX, and Discover ) will be accepted. Pick up registration materials at the Registration Desk when you arrive. Cancellation & refund requests will be honored if received in writing no later than July 24, 2018, and are subject to a $50 fee. Any other approved dispositions will also be assessed a $50 fee. 45

46 IEW 2019 The First IRPS and IEW Dual Convention! March 31- April 4, International ESD Workshop (IEW) Hyatt Regency Monterey One Old Golf Course Road Monterey, CA, USA Setting the Global Standards for Static Control! EOS/ESD Association, Inc Turin Rd., Bldg. 3, Rome, NY , USA PH

47 EOS/ESD Symposium and Exhibits September 15-20, 2019 Riverside Convention Center, Riverside, CA, USA Setting the Global Standards for Static Control! EOS/ESD Association, Inc Turin Rd., Bldg. 3, Rome, NY , USA PH