Accellera Overview February 27, Lu Dai Accellera Chairman

Transcription

1 Accellera Overview February 27, 2017 Lu Dai Accellera Chairman

2 Welcome Agenda About Accellera Current news Technical activities IEEE collaboration 2

3 Accellera Systems Initiative Our Mission To provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. 3

4 Broad Industry Support Corporate Members 4

5 Broad Industry Support Associate Members 5

6 Global Presence DVCon U.S. SystemC Evolution Day DVCon Europe Design Automation Conference Verification & ESL Forum DVCon India SystemC Japan DVCon China 6

7 Agenda About Accellera Current news Technical activities IEEE collaboration 7

8 Accellera News Standards - IEEE Approves UVM 1.2 as IEEE Accellera relicenses SystemC reference implementation under Apache 2.0 Outreach - First DVCon China to be held April 19, Get IEEE free standards program extended 10 years/10 standards Awards - Thomas Alsop receives 2017 Technical Excellence Award for his leadership of the UVM Working Group - Shrenik Mehta receives 2016 Accellera Leadership Award for his role as Accellera chair from

9 DVCon Global Presence 29 th Annual DVCon U.S. 4 th Annual DVCon Europe 4 th Annual DVCon India 1 st DVCon China 9

10 Agenda About Accellera Current news Technical activities IEEE collaboration 10

11 Accellera Systems Initiative Board of Directors Promotions Committee Technical Committee Administration Interface SystemVerilog- AMS OVL IP-XACT SystemC Language SystemC AMS Multi Language OCP IP Tagging SystemRDL UVM UCIS Schema WG Registers Extensions SC/TLM Evolution SC Datatypes SystemC TLM SystemC Synthesis SystemC CCI Supported IEEE Working Groups Portable Stimulus User Group Compliance SystemC Verification 1076 VHDL 1800 SystemVerilog UVM 1801 UPF 1666 SystemC SystemC AMS 1685 IP-XACT 11

12 Ongoing Technical Activities Open Verification Library (OVL) Verilog-AMS (V-AMS) 2.4 Standard Co-Emulation Modeling Interface (SCE-MI) 2.3 Unified Coverage Interoperability Standard (UCIS) 1.0 IP-XACT - Update of IEEE 1685 Issues and Vendor Extensions Intellectual Property (IP) Tagging 1.0 Multi-Language (ongoing) Portable Stimulus (ongoing) SystemVerilog-AMS (ongoing) SystemC Synthesis SystemC Analog Mixed-Signal (AMS) 2.0 SystemC LRM and Examples (includes TLM 2.0) SystemRDL 1.0 Current Standards and Activities Open Source Companions: - UVM Reference Implementation SystemC Proof of Concept Library SystemC Verification Library (SCV) UVM-SystemC 1.0-alpha version Accellera Systems Initiative, Inc.

13 Agenda About Accellera Current news Technical activities IEEE collaboration 13

14 Strong Partnership with IEEE IEEE Get program allows access to EDA & IP standards worldwide Download for free SystemC SystemC AMS IP-XACT SystemVerilog UVM coming soon! UPF Ongoing collaboration with the IEEE Standards Association SystemC Language SystemC Analog Mixed-Signal (AMS) IP-XACT SystemVerilog Universal Verification Methodology (UVM) Unified Power Format (UPF) Property Specification Language (PSL) 14

15 IEEE Standards Access at No Charge Accellera relationship with the IEEE-SA Accellera will release 10 standards for 10 years under an extended Get IEEE program More than 83,000 downloads to date! Cumulative Downloads

16 Advancing Standards Together Share your experiences - Visit and register to post on forums at forums.accellera.org Show your support - Record your adoption of standards Become an Accellera member - Join working groups 16

17 THANK YOU Download a copy of this presentation at Thank you to our Global Sponsors 17