Annual EOS/ESD Symposium & Exhibits

Transcription

1 37 th Annual EOS/ESD Symposium & Exhibits The International Technical Forum on Electrical Overstress and Electrostatic Discharge September 27-October 2, 2015 Peppermill Resort Hotel Reno, NV IEEE Co-sponsored by IEEE, The Electron Devices Society, EMC Society, and Reliability Society. Setting the Global Standards for Static Control! EOS/ESD Association, Inc Turin Rd., Bldg. 3 Rome, NY , USA PH info@esda.org

2 General Chair s Welcome Dear Colleagues, On behalf of the EOS/ESD Association, Inc. and the 2015 Symposium Steering Committee, I would like to extend a warm welcome to the 37 th EOS/ESD Symposium, held at the Peppermill Resort Hotel in Reno, Nevada. Following its long tradition, the 2015 EOS/ESD Symposium will address the latest research on EOS and ESD protection in the rapidly changing world of electronics. With the emergence on the internet of things on the horizon, systems must become ever more reliable. Driving costs down so that electronics become even more pervasive requires high-yield manufacturing and assembly, with low tolerance for excursions. The technology to make all of this happen continues to evolve. FinFETs are becoming common place. 3D and 2.5D integration is reaching manufacturing maturity. Performance prediction through simulation and verification checks must continue to advance to a greater degree of thoroughness and accuracy. The 2015 EOS/ESD Symposium addresses these matters and more through tutorials, workshops, technical sessions, and invited talks. The technical paper sessions are the heart of the symposium. A total of 55 reviewed papers will be presented. Sessions this year cover ESD in advanced technologies, factory control, system-level ESD, ESD in RF and power devices, testers and testing methods, 3D stacking, EDA, and TCAD. I would like to thank all authors who submitted abstracts, expanded them into full papers, prepared presentations, and revealed their work to all of us. Behind the authors is our highly dedicated technical program committee, which reviews submissions and mentors them to bring out the best in every paper and presentation. As is our tradition, the keynote presentation kicks off the technical portion of the symposium. Texas A&M Professor Richard Orville, Director of the National Oceanographic and Atmospheric Association and National Weather Service Cooperative Institute for Applied Meteorological Studies, will focus on his research in lightning detection and mapping. Preceding the keynote address on Tuesday morning is our awards breakfast, where awards from the 2014 Symposium, including Best Paper and Best Student Paper Awards, the Symposium Outstanding Paper Award, and the Friendship Awards will be presented. A series of invited papers will give an overview of recent technical trends and specific applications with impact on ESD. Alan Righter will present a comprehensive overview of the continued evolution of CDM design, modeling, and testing standards. Christoph Thienel puts the emphasis back in the EOS portion of the symposium with his year in review presentation on EOS and ESD developments in the automotive industry, where absolute reliability is required for user safety. Six symposium workshops offer an interactive forum for sharing experiences, searching for solutions, and discussing nagging questions. Centered on relevant and timely technical topics, each workshop allows participants the opportunity to learn from colleagues and take in their perspectives through an informal discussion environment. You may bring your questions directly to the workshops or submit them to workshop moderators in advance. A dedicated team has been working hard all year to prepare the tutorial program. Many tutorials have been refreshed with updated material. If you haven t taken a tutorial for a few years, now is a good time to circle back to bring yourself up to date with the latest in your field or explore a new area. I also want to express a warm welcome to our exhibitors. Without them, the symposium would not be possible. Many of them are attendees and have been exhibitors for many years. I am looking forward to an intensive exchange and discussion in the exhibitors hall during the welcome reception on Monday evening and the days following. Showcases at the beginning of technical sessions will highlight news from several exhibitors. I encourage all attendees to visit the exhibit hall to get first-hand information on newest products for daily ESD work. For this 2015 symposium, I wish that all participants come away with increased understanding, new and renewed contacts, and that all contributors leave with a sense of pride in how they have advanced the knowledge in the field of ESD. Sincerely, Warren Anderson Synopsys, Inc EOS/ESD Symposium General Chairman 2

3 General Information...4 Registration, Fees, Hours...4 Welcome Reception...5 Annual Meeting and Awards Breakfast...5 Professional and Technical Women s Reception... 5 Local Chapter Reception...5 Schedule Keynote...8 Professional Certification Tutorial Tracks Emerging Technology Seminars...12 ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar)...12 Tutorials Technical Sessions Workshops Exhibits...32 ESDA Officers, Board of Directors, and HQ Staff Symposium Committees...33 Technical Program Committee...33 Hotel Reservations & Information...34 Registration Form

4 General Information On-Site Registration Hours Registration will be open at the following times: Sunday, September 27 7:30 a.m. - 5:00 p.m. Monday, September 28 7:30 a.m. - 5:00 p.m. Tuesday, September 29 7:30 a.m. - 5:00 p.m. Wednesday, September 30 7:30 a.m. - 5:00 p.m. Thursday, October 1 7:30 a.m. - 5:00 p.m. Save by registering in advance! This will facilitate your registration upon your arrival at the Symposium. Early registration and member discounts* are valid only if received no later than Aug. 14, Symposium $800 (Includes technical sessions, workshops, and exhibits) Early Registration Fees valid until Aug. 14, 2015 EOS/ESD Association, Inc. Members* $600/Non-Members $700 Tutorials $710 (per day) (Sunday, Monday, OR Thursday (Full Day)) Early Registration Fees valid until Aug. 14, 2015 EOS/ESD Association, Inc. Members* $510/Non-Members $610 Bundled Fees $2,465 (Symposium plus Sun., Mon., and Thurs. full tutorial days) Early Registration Fees valid until Aug. 14, 2015 EOS/ESD Association, Inc. Members* $1,785/Non-Members $2,165 Emerging Technology Seminars $95 (Attendance limited to first 50 registrants) These seminars are not included in the bundled fee. ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) $1,710 (Attendance limited to first 30 registrants) This seminar is not included in the bundled fee. Early Registration Fees valid until Aug. 14, 2015 EOS/ESD Association, Inc. Members* $1,510/Non-Members $1,610 *Membership discounts apply to those who participate as members all year long and are current at the opening of symposium registration. Memberships processed after this date will not apply. You will receive a complimentary 2016 membership with your Symposium registration which will allow you to enjoy the full benefits of membership in Register 5 or more people from one company at the same time and save $100 per person. Please contact the EOS/ESD Association, Inc. prior to registering. Student Fees The EOS/ESD Symposium offers a fifty percent discount for full-time students. Proof of enrollment required. Student fees apply only to symposium or tutorial registration and do not apply to bundled fees, ANSI/ ESD S20.20 seminar, or emerging technology seminars. General Information Symposium Proceedings Each paid registrant receives one electronic copy of the proceedings. Tutorial Notes Customized, full color tutorial notes will be provided to each tutorial registrant. Hospitality Suites To maintain the objectives of the Symposium, the EOS/ ESD Association, Inc. encourages all exhibitors and guest organizations to schedule their hospitality and other social events at times that do not conflict with the Symposium presentations and educational activities. Age Limits No one under 18 years of age will be admitted to the exhibit hall. Unauthorized Solicitation Solicitation of business on the premises during the EOS/ ESD Symposium by manufacturers or others who are not participating as exhibitors is prohibited. Recording Video and/or audio recording of Symposium events is prohibited without the prior written authorization of the EOS/ESD Association, Inc.. 4 Register Online!

5 Welcome Reception A welcome reception for all attendees will be held on Monday, September 28 th, at 5:00 p.m. in the exhibit hall. Network with your colleagues, share your ESD work experiences with others, view the exhibits, or simply pass the time meeting new people and making new friends. The 2015 Steering Committee will greet you and answer any questions regarding the Symposium. Annual Meeting and Awards Breakfast The annual meeting and awards breakfast for all registered attendees and exhibitors will be held Tuesday, September 29 th, at 7:30 a.m. Following breakfast, General Chair Warren Anderson will officially open the Symposium. Vice General Chair Melanie Etherton will present the 2014 EOS/ESD Symposium paper awards. Technical Program Chair Junjun Li will cover highlights of the 2015 technical program. Association President Terry Welsher will present the Association s annual report. Awards Chairman, Charvaka Duvvury, will present the 2015 Association awards. Professional and Technical Women s Reception The Professional and Technical Women s Reception provides a friendly environment where women in the field of ESD can network and share work experiences. This year s reception will be held on Monday, September 28 th, from 5:00 to 6:00 p.m. Local Chapter Reception This new reception for the ESDA Local Chapters provides an opportunity to network and share educational experiences. The reception will be held on Tuesday, September 29 th, from 4:30 to 5:30 p.m. We look forward to seeing all Local Chapter members there! 5

6 2015 Symposium Schedule SUNDAY, SEPTEMBER 27, 2015 Registration 7:30 a.m. - 5:00 p.m. S20.20 Seminar 8:00 a.m. - 5:00 p.m. FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) (PrM) (Day 1) Tutorials 8:30 a.m. - 4:30 p.m. FC100: ESD Basics for the Program Manager (PrM) 8:30 a.m. - 12:00 p.m. DD110: ESD from Basics to Advanced Protection Design (DD) 8:30 a.m. - 12:00 p.m. DD200: Charged Device Model Phenomena, Design, and Modeling (DD) 8:30 a.m. - 12:00 p.m. FC215: Device Technology and Failure Analysis Overview (PrM) 8:30 a.m. - 10:00 a.m. FC260: Electrostatic Attraction 10:30 a.m. - 12:00 p.m. FC161: Perfect ESD Storm 1:00 p.m. - 4:30 p.m. DD201: ESD Protection and I/O Design 1:00 p.m. - 4:30 p.m. DD302: Troubleshooting On-Chip ESD Failures (DD) 1:00 p.m. - 4:30 p.m. FC165: Novel Methods for Fixing ESD Issues in the Factory for Both Electronics & Explosive Products NEW 1:00 p.m. - 4:30 p.m. DD/FC122: Use of the Digital Sampling Oscilloscope for ESD Measurements Study Session 5:00 p.m. - 6:00 p.m. Calculations and ESD Scenarios Review for ESD Program Manager Exam Preparation (STUDY SESSION) MONDAY, SEPTEMBER 28, 2015 Registration 7:30 a.m. - 5:00 p.m. S20.20 Seminar 8:00 a.m. - 5:00 p.m. FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) (PrM) (Day 2) Tutorials 8:30 a.m. - 4:30 p.m. FC101: How To s of In-Plant ESD Auditing and Evaluation Measurements (PrM) 8:30 a.m. - 12:00 p.m. DD/FC230: System Level ESD/EMI: Principles, Design Troubleshooting, and Demonstrations 8:30 a.m. - 12:00 p.m. FC361: Class 0A Devices & Boards - ESD Controls and Auditing Measurements 8:30 a.m. - 12:00 p.m. FC362: Using Different Air Ionization Technologies and Measuring Process Effects NEW 8:30 a.m. - 12:00 p.m. DD/FC221: Correlation of ESD Robustness and Handling Threats 8:30 a.m. - 10:00 a.m. DD204: ESD Design in HV Technologies 10:30 a.m. - 12:00 p.m. DD381: Electronic Design Automation (EDA) Solutions for ESD 1:00 p.m. - 4:30 p.m. DD231: Integrated ESD Device and Board Level Design 1:00 p.m. - 4:30 p.m. DD103: An Overview of Integrated Circuit ESD: The ESD Threat, Testing, Design Concepts, and Debugging 1:00 p.m. - 4:30 p.m. FC360: Electrical Overstress (EOS) in Manufacturing and Test 1:00 p.m. - 4:30 p.m. FC261: Electrical Fields - Practical Considerations for the Factory REVISED 1:00 p.m. - 2:30 p.m. DD240: ESD Device Qualification Testing NEW 3:00 p.m. - 4:30 p.m. DD213: ESD, EOS, and Latch-up Failure Analysis for Designers Emerging Technology Seminars 1:00 p.m. - 2:30 p.m. Cell Phone RF Front Ends: Increasing Complexity and the Enhanced Capabilities That Are Driving it NEW 3:00 p.m. - 4:30 p.m. ESD Induced Display Problems by Spark-less Discharges NEW Reception 5:00 p.m. - 6:00 p.m. Professional and Technical Women s Reception Welcome Reception 5:00 p.m. - 9:00 p.m. Exhibits Open TUESDAY, SEPTEMBER 29, 2015 Registration 7:30 a.m. - 5:00 p.m. Awards Breakfast 7:30 a.m. - 9:45 a.m. Annual Meeting and Awards Breakfast Keynote 9:00 a.m. - 9:45 a.m. Electrostatic Discharges in the Atmosphere; Lightning Mapping: Past, Present, and Future Exhibits Open 9:30 a.m. - 5:30 p.m. Technical Sessions 10:10 a.m.-10:20 a.m. Exhibitor Showcase in Sessions 1A and 1B 10:20 a.m.-12:00 p.m. 1A: ESD Protection in Advanced Technologies 10:20 a.m.-12:00 p.m. 1B: Factory Control I 1:00 p.m. - 1:10 p.m. Exhibitor Showcase in Sessions 2A and 2B 1:10 p.m. - 2:50 p.m. 2A: ESD Design in RF and Power Devices 1:10 p.m. - 2:50 p.m. 2B: System Level ESD Design 3:45 p.m. - 5:00 p.m. 3A: ESD Checking and Verification 3:45 p.m. - 5:00 p.m. 3B: ESD Failure Case Study Reception 4:30 p.m. - 5:30 p.m. Local Chapter Reception Study Session 5:00 p.m. - 6:00 p.m. Calculations and ESD Scenarios Review for ESD Program Manager Exam Preparation (STUDY SESSION) 6

7 TUESDAY, SEPTEMBER 29, 2015 continued Workshops A 5:30 p.m. - 7:00 p.m. A1: Strategies to Address Latch-up Test Program Complexity in Advanced Mixed Signal ICs A2: Best Practices for ESD Robust SoC Integration of Commercial IP A3: Implications of the New ANSI/ESD S2020 Specification WEDNESDAY, SEPTEMBER 30, 2015 Registration 7:30 a.m. - 5:00 p.m. Exhibits Open 8:30 a.m. - 1:30 p.m. Technical Sessions 8:00 a.m. - 8:10 a.m. Industry Council Update 8:10 a.m. - 8:50 a.m. Year in Review: The Continued Evolution of CDM in Manufacturing, Design, Modeling, and Testing Standards 9:00 a.m. - 9:10 a.m. Exhibitor Showcase in Sessions 4A and 4B 9:10 a.m. - 10:25 a.m. 4A: TCAD Design and Simulation 9:10 a.m. - 10:25 a.m. 4B: Tester and Testing Method I 11:20 a.m. - 12:10 p.m. 5A: 3D Chip Stacking ESD Protection 11:20 a.m. - 12:10 p.m. 5B: Factory Control II 1:20 p.m. - 3:00 p.m. 6A: ESD Simuation and Verification 1:20 p.m. - 3:00 p.m. 6B: Factory Control III 3:20 p.m. - 5:00 p.m. 7A: HV ESD Clamp Design 3:20 p.m. - 5:00 p.m. 7B: System Level ESD Testing Workshops B 5:30 p.m. - 7:00 p.m. B1: What Should Foundries Include in Their PDKs to Better Support Custom ESD Design? B2: Is HBM-1000V/CDM-250V Now the Industry Default Qualification Target for IC Components? B3: Component System Level ESD Design; Efforts by Auto Tier 1 s to Define Standard Tests THURSDAY, OCTOBER 1, 2015 Registration 7:30 a.m. - 5:00 p.m. Technical Sessions 8:00 a.m. - 8:40 a.m. Year in Review: Understanding EOS in Automotive Industry 8:50 a.m. - 10:30 a.m. 8A: Tester and Testing Method II 10:50 a.m. - 12:05 a.m. 9A: ESD Testing and Failure Analysis Tutorials 9:00 a.m. - 12:30 p.m. FC164: Costly Controversial ESD Myths 9:00 a.m. - 12:30 p.m. FC110: Cleanroom Considerations for the Program Manager (PrM) 9:00 a.m. - 12:30 p.m. FC210: ESD Standards Overview for the Program Manager (PrM), (inarte) 9:00 a.m. - 10:30 a.m. DD117: TCAD Fundamentals 9:00 a.m. - 10:30 a.m. DD112: Latch-up Fundamentals (DD) 11:00 a.m. - 12:30 p.m. DD319: Physical Process, Device, and Circuit Simulation (TCAD) Methodologies in Application to Industrial ESD Research and Design 11:00 a.m. - 12:30 p.m. DD222: Practical Aspects of Latch-Up for Low Voltage CMOS: Design Rules, Layout Floor Planning, and Test 1:30 p.m. - 5:00 p.m. DD220: Transmission Line Pulse (TLP) Basics and Applications (DD) 1:30 p.m. - 5:00 p.m. DD301: SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits (DD) 1:30 p.m. - 5:00 p.m. FC201: ESD - A Surprisingly Frequent Root Cause of Device Failure 1:30 p.m. - 5:00 p.m. DD/FC380: Electrostatic Calculations for the Program Manager and the ESD Engineer (PrM), (inarte) 1:30 p.m. - 5:00 p.m. FC200: Packaging Principles for the Program Manager (PrM) FRIDAY, OCTOBER 2, :00 a.m. - 5:00 p.m. Device Design Certification Exam 8:00 a.m. - 5:00 p.m. Program Manager Certification Exam 8:00 a.m. - 5:00 p.m. inarte Certification Exams 7

8 Tuesday September 29 th 9:00 a.m. - 9:45 a.m. 8Keynote Abstract: The United States is covered by lightning networks that include the National Lightning Detection Network (NLDN) and Lightning Mapping Arrays (LMA), which record most of the over 100 million flashes that occur annually over the USA. These networks provide us with flash counts or multiplicity, peak current estimates and stroke polarity. In addition to these instruments, we use high-speed cameras operating up to 100,000 frames per second to record the microsecond propagation characteristics of luminous spectroscopic features that travel near the speed of light. Our spectroscopic observations reveal lightning characteristics that include channel temperatures over 30,000 to 40,000 o K, peak pressures over 8 atmospheres, which produce thunder, and complete dissociation and ionization of the air molecules within the channel. The luminous cloud-to-ground features identified to-date include, stepped leaders, return strokes, dart leaders, M-components, recoil leaders, and polarity. For the first time, our LMA networks allow us to track the lightning channels in three dimensions giving us the knowledge, when combined with radar observations, to assist in predicting the first and last lightning to occur in a thunderstorm. Over the past few decades lightning information has been available on the Internet and we have witnessed a reduction in the annual deaths in the USA by a factor of two, from approximately 100 to 50 deaths per year. Electrostatic Discharges in the Atmosphere; Lightning Mapping: Past, Present, and Future Dr. Richard Orville, Research Professor and Director Cooperative Institute for Applied Meteorological Services (CIAMS) Department of Atmospheric Sciences, Texas A&M University College Station, TX Phone: rorville@tamu.edu Richard Orville received his A.B. degree in Physics from Princeton University in 1958 and the M.S. degree and Ph.D. degree in atmospheric physics from the University of Arizona in He joined the Westinghouse Research Laboratories near Pittsburgh in 1966 and performed two years of spectroscopic research on laboratory long sparks and lightning field studies in Lugano, Switzerland. In Lugano, Richard Orville recorded the first lightning spectra of lightning strikes to the instrumented towers on Mte. San Salvatore where Professor Karl Berger of the Swiss Institute of Technology, Zurich, routinely measured lightning peak currents. In 1968, he began a university career at the State University of New York at Albany and moved to the Texas A&M University (1991) while pursuing research supported by the National Science Foundation, the National Aeronautics and Space Administration, the Electric Power Research Institute, and the National Oceanic and Atmospheric Administration.

9 Certification EOS/ESD Association, Inc. Professional Certification The EOS/ESD Association, Inc. offers professional certification for ESD control program managers and device design technical specialists. ESD Certified Professional-Program Manager The impact of the ANSI/ESD S20.20 ESD control program standard on the global industry has been extraordinary. As a result, the Association recognizes the need to offer a certification program for individuals that are involved in designing, implementing, managing, and auditing ESD control programs in their facilities. The program manager certification program serves that purpose. In addition, the needs of the technical community for certification of various technical specialists are apparent. Requirements for certification include attending required prerequisite tutorials and passing a final exam. All of the prerequisite courses may not be available in the 2015 Symposium tutorial program. Details of the certification program are also available in the registration area. The preferred tutorial sequence for the program manager curriculum is: COURSE TITLE FACE TO FACE TUTORIAL ONLINE FC100 ESD Basics for the Program Manager Symposium, Sunday, Sept. 27 FC101 How To s of In-Plant ESD Auditing and Evaluation Measurements Symposium, Monday, Sept. 28 FC110 Cleanroom Considerations for the Program Manager Symposium, Thursday, October 1 Available Online On-Demand FC120 Air Ionization Issues and Answers for the Program Manager Available Online On-Demand FC200 Packaging Principles for the Program Manager Symposium, Thursday, October 1 Available Online On-Demand FC210 ESD Standards Overview for the Program Manager Symposium, Thursday, October 1 Available Online On-Demand DD/FC130 System Level ESD/EMI: Testing to IEC and Other Standards Available Online On-Demand FC215 Device Technology and Failure Analysis Overview Symposium, Sunday, Sept. 27 Available Online On-Demand FC340 ESD Program Development & Assessment (ANSI/ESD S20.20 Seminar) FC380 Electrostatic Calculations for the Program Manager and the ESD Engineer Symposium, Sunday-Monday, Sept Symposium, Thursday, October 1 Available Online On-Demand ESDA Certification Exam The certified professional program manager exam will be held on Friday, October 2 nd. To take the exam, applicants must have a registration form on file with the EOS/ESD Association, Inc. headquarters complete with a $50 filing fee prior to the Symposium. Applicants must also have completed all required courses and had their eligibility verified by the ESD Association. An exam fee of $60 is applicable (in addition to the filing fee). Please note: each of the test sections include essay questions that require a good understanding of English. Up to 50% of the grade in each section may involve essay and short written answers. The exam is open book. You may bring any reference materials, including, but not limited to, books, standards, and tutorial notes. You may also bring a calculator and computer. No cell phones, internet connections, or sharing of reference materials is allowed. Offer to Certified inarte Engineers: The EOS/ESD Association, Inc. is offering inarte certified ESD engineers the opportunity to take the program manager certification exam without taking all required courses. Simply show a current in- ARTE card, pay the exam fee, and take the exam. Please note that the program manager exam covers more areas than the inarte exam and may be more difficult. inarte Certification Exam The inarte certification exams for ESD engineers and ESD technicians will be offered on Friday, October 2nd. Applicants must complete an application form and submit the application fee to inarte prior to the exam. For more information visit www. narte.org/h/aboutnarte.asp#programs. 9

10 Certification ESD Certified Professional-Device Design ESD device design certification was developed for individuals that are involved in designing, testing, characterizing, and implementing improved ESD protection designs. Device design certification demonstrates knowledge, experience, and competency in the area of ESD design and test for device protection. Requirements for certification include attending required prerequisite tutorials and passing a final exam. All of the prerequisite courses may not be available in the 2015 Symposium tutorial program. Details of the certification program are also available in the registration area. The preferred tutorial sequence for the device design curriculum is: COURSE TITLE FACE TO FACE TUTORIAL ONLINE DD110:Overview of ESD and Related Effects for Device/Design Symposium, Sunday, Sept. 27 DD301: SPICE-Based ESD Protection Design Utilizing Diodes and Active MOS- Symposium, Thursday, October 1 FET Rail Clamp Circuits DD211: EOS/ESD Failure Models and Mechanisms DD102: On-chip ESD Protection in RF Technologies DD200: Charged Device Model Phenomena, Design, and Modeling Symposium, Sunday, Sept DD112: Latch-up Fundamentals Symposium, Thursday, October DD300: Circuit-Level Modeling and Simulation of On-Chip Protection DD302: Troubleshooting On-Chip ESD Failures DD120: Device Testing--IC Component Level: HBM, CDM, MM, and TLP DD311: Impact of Technology Scaling on ESD High Current Phenomena and Implications for Robust ESD Design DD220: Transmission Line Pulse (TLP) Basics and Applications DD/FC130: System Level ESD/EMI: Testing to IEC and other Standards Symposium, Sunday, Sept. 27 Symposium, Thursday, October 1 Available Online On-Demand May 2015 Available Online On-Demand August 2015 Available Online On-Demand August 2015 Available Online On-Demand ESDA Certification Exams The certified professional device design exam will be held on Friday, October 2 nd. To take the exam, applicants must have a registration form on file with the EOS/ESD Association, Inc. headquarters complete with a $50 filing fee prior to the Symposium. Applicants must also have completed all required courses and had their eligibility verified by the ESD Association. An exam fee of $60 is applicable (in addition to the filing fee). Please note: each of the test sections include essay questions that require a good understanding of English. Up to 50% of the grade in each section may involve essay and short written answers. The exam is open book. You may bring any reference materials, including, but not limited to, books, standards, and tutorial notes. You may also bring a calculator and computer. No cell phones, internet connections, or sharing of reference materials is allowed. 10

11 Tutorial Tracks Day Track Quarter Day Class 8:30-10:00 (Thur. 9:00-10:30) Sunday Factory Control & Testing Seminar 8:00-5:00 Full Day Class 8:30-4:30 Half Day Class 8:30-12:00 (Thur. 9:00-12:30) Half Day Class 1:00-4:30 (Thur. 1:30-5:00) Quarter Day Class 10:30-12:00 (Thur. 11:00-12:30) Quarter Day Class 1:00-2:30 Quarter Day Class 3:00-4:30 FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) FC215: Device Technology and Failure Analysis Overview FC260: Electrostatic Attraction FC100: ESD Basics for the Program Manager FC161: Perfect ESD Storm NEW FC165: Novel Methods for Fixing ESD Issues in the Factory for Both Electronics & Explosive Products DD/FC122: Use of the Digital Sampling Oscilloscope for ESD Measurements System Level ESD ESD for IC Design DD110: ESD from Basic to Advanced Protection Design DD200: Charged Device Model Phenomena, Design, and Modeling DD302: Troubleshooting On-Chip ESD Failures DD201: ESD Protection and I/O Design Monday Factory Control & Testing FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) FC101: How To s of In-Plant ESD Auditing and Evaluation Measurements FC361: Class 0A Devices & Boards - ESD Controls and Auditing Measurements NEW FC362: Using Different Air Ionization Technologies and Measuring Process Effects FC360: Electrical Overstress (EOS) in Manufacturing and Test Revised FC261: Electrical Fields - Practical Considerations for the Factory System Level ESD ESD for IC Design DD-FC230 - System Level ESD/EMI Principles, Design Troubleshooting, & Demonstrations DD/FC221: Correlation of ESD Robustness and Handling Threats DD231: Integrated ESD Device and Board Level Design DD103: An Overview of Integrated Circuit ESD: The ESD Threat, Testing, Design Concepts and Debugging ESD Technology DD204 - ESD Design in HV Technologies DD381 - Electronic Design Automation (EDA) Solutions for ESD NEW DD240: ESD Device Qualification Testing DD213: ESD, EOS, and Latch-up Failure Analysis for Designers Thursday Factory Control & Testing FC164: Costly Controversial ESD Myths FC110: Cleanroom Considerations for the Program Manager FC210: ESD Standards Overview for the Program Manager FC201: ESD - A Surprisingly Frequent Root Cause of Device Failure DD/FC380: Electrostatic Calculations for the Program Manager and the ESD Engineer FC200: Packaging Principles for the Program Manager ESD Technology DD117: TCAD Fundamentals DD112: Latch-up Fundamentals DD220: Transmission Line Pulse (TLP) Basics and Applications DD319: Physical Process, Device, and Circuit Simulation (TCAD) Methodologies in Application to Industrial ESD Research and Design DD222: Practical Aspects of Latch-Up for Low Voltage CMOS: Design Rules, Layout Floor Planning, and Test DD301: SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits Device Design Certification Courses Program Manager Certification Courses inarte Recommended Preparation Courses 11

12 Seminars EMERGING TECHNOLOGY SEMINARS Emerging technology seminars are offered in addition to the regular tutorials at the 2015 EOS/ESD Symposium. The emerging technology seminars are targeted to experienced ESD designers and technologists who would like to learn more about upcoming technologies to better assess the impact on ESD design and ESD protection concepts. They will provide a condensed and first hand overview of the technology with clear indications of ESD and reliability relevant aspects. This is a unique chance to get important information without needing to attend general semiconductor technology conferences. The two seminars below are being presented by leading experts in their field and will give the attendees excellent insight into RF front-end designs and touch screens. MONDAY SEPTEMBER 28 NEW Cell Phone RF Front Ends: Increasing Complexity and the Enhanced Capabilities That Are Driving it 1:00 p.m. - 2:30 p.m. Instructor: Paul Brey, Qorvo NEW ESD Induced Display Problems by Spark-less Discharges 3:00 p.m. - 4:30 p.m. Instructor: David Pommerenke, Missouri University of Science and Technology As cellular phones have become ubiquitous, and data throughput demands have continued to grow seemingly without bounds, the cellular industry has risen to the occasion by rolling out new standards, frequency bands, and many exciting new features. This has resulted in a profound increase in the complexity and engineering challenges for the RF front end within a cell phone. This presentation traces the development of the front end architectures, from the early days until today, summarizes and explains the new services and features which present today s challenges, and discusses their impact on the RF architecture. Topics explained will include Uplink and Downlink Carrier Aggregation, RX Diversity and MIMO, Envelope Tracking, LTE Advanced and LTE-U, Dynamic Antenna Tuning and Matching, Acoustic RF filtering, and recent developments in Chip-to Chip Digital Communications Standards. Touchscreens and the underlying display structure is exposed to numerous, ESD discharge every day. These discharges couple energy to the structures inside the display, the connecting flex cables and the body of the phone. While a good high voltage design can prevent discharges to the inner structure of the display it is not possible to prevent discharges to the glass surface. Those discharges do not cause any visible sparks, however, they cause corona charging on the surface. The corona discharge spreads at about 1mm/ns to areas as large as 30mm diameter. The corona charge causes displacement current through the glass which couple to the internal structures. The talk will illustrate this corona charging, show the magnitudes and parameter dependence such as the effect of glass type and thickness. Further, initial modeling results for the coupling into the phone structure will be presented. ANSI/ESD S20.20 SEMINAR T SUNDAY AND MONDAY SEPTEMBER FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) 8:00 a.m. - 5:00 p.m. Instructors: David E. Swenson, Affinity Static Control Consulting, LLC; Kevin Duncan, Seagate Technology Certification: PrM The S20.20 Seminar is intended to bring all the aspects of the Program Manager Curriculum to a final focal point. The concepts of electrostatic control are discussed within the context of designing, implementing and maintaining an effective ESD control program plan that meets the requirements of the standard. Preparing a documented ESD Control Program Plan that can withstand a 3rd party ISO9000 Certification Body is a major element of the certification process. Students are required to participate in numerous activities in this seminar to help acquaint them with the concepts involved in designing an ESD control program plan. The following topics are covered in this course: Overview of ANSI/ESD S20.20 How to approach an assessment Administrative elements ESD program assessment ESD program techniques for different applications Technical elements Overview of the assessment process The audit checklist and follow-up questions 12 Customized, full color tutorial notes will be provided to each tutorial registrant

13 Tutorials Tutorials: Featuring basic, intermediate, and advanced courses, the tutorial program is organized along parallel tracks to allow attendees to easily create an individual educational experience in specific categories of interest. SUNDAY SEPTEMBER 27 FC100: ESD Basics for the Program Manager 8:30 a.m. - 4:30 p.m. Instructor: Stephen Halperin, SH&A/Prostat Corporation Certification: PrM This presentation is a comprehensive introduction to the fundamentals of ESD causes and control. ESD Basics is a full-day seminar consisting of three presentation sections. Part 1 includes an overview of ESD impact on industry, with detailed explanations of charge generation, field measurement, the role of capacitance and voltage, charge measurement, and charge decay. Part 2 focuses on general explanations and illustrations of device failure mechanisms, including Human Body Model, Charge Device and Field Induction Models, and explains the Machine Model. Part 3 is concerned with protecting ESD sensitive devices and assemblies, defining the Electrostatic Protected Area (EPA), understanding various ESD control elements and material selection, and includes a brief introduction to ANSI/ESD S20.20 ESD Program Development criteria. Several demonstrations and opportunities for discussion make this an interesting introduction to ESD causes and control. No previous ESD experience necessary. DD110: ESD from Basics to Advanced Protection Design 8:30 a.m. - 12:00 p.m. Instructor: Charvaka Duvvury, ESD Consulting LLC Certification: DD This course gives a comprehensive overview from ESD basics to ESD design principles covering up to the latest silicon technologies appealing to a variety of engineers from design to process technology, and failure analysis to quality. The attendee will have an in-depth understanding of the principles of ESD Device/Design along with a full perception of what it takes to address almost every kind of design scenario, how to apply rules of thumb for successful design, knowledge of lessons learned from case studies, and empowerment to communicate with customers on ESD quality issues. DD200: Charged Device Model Phenomena, Design, and Modeling 8:30 a.m. - 12:00 p.m. Instructors: Michael Chaine, Micron Technology, Inc.; Melanie Etherton, Freescale Semiconductor, Inc. Certification: DD This course teaches basic ESD circuit design concepts and ideas required to design ESD protection for charge device model (CDM) ESD tests. The course covers a brief history of CDM ESD development, charge and discharge physics, characterization methods, CDM failures mechanisms, and CDM design-in strategies. CDM ESD circuit design approaches and simulation setups for CDM failure debugging are presented in this tutorial on the basis of case studies. Insight into CDM circuit simulation requirements and physical aspects of the CDM ESD phenomenon that are important for reproducing the event with circuit simulation will be taught and modeling approaches for CDM specific device physical effects necessary for accurate circuit simulation will be introduced. This course also teaches methods for simplified CDM circuit simulations where detailed information is either not available or too complex to simulate. The course focuses on what type of circuits fail during a CDM discharge event and teaches the different types of ESD design circuit strategies that can be applied to protect those circuits. This class covers basic to advanced topics for CDM ESD design, but the student is assumed to already have a basic understanding of the CDM test method. FC215: Device Technology and Failure Analysis Overview 8:30 a.m. - 12:00 p.m. Instructor: Jim Vinson, Intersil Corporation Certification: PrM This tutorial is designed to give an overview of ESD protection technology and design, as well as an overview of the debug techniques used when a circuit fails to meet ESD performance requirements. The three major areas addressed are 1) a general overview of ESD, 2) circuit protection techniques, and 3) failure analysis. Failure analysis is the key to identifying and correcting weaknesses in ESD designs. The tutorial is NOT intended to turn the student into an ESD device or circuit designer nor a failure analyst. Rather, it is meant for program managers and other support personnel who are involved in the product development process to gain a better understanding of the language and challenges encountered supporting ESD robustness in new designs. After completing this tutorial, the student will be exposed to the key specifications governing ESD robustness and the common device architectures used to provide that robustness. The tutorial will include real world examples of protection designs and electrical characterization of those designs, as well as go through the tools and techniques used to debug a design. Customized, full color tutorial notes will be provided to each tutorial registrant 13

14 Tutorials FC260: Electrostatic Attraction 8:30 a.m. - 10:00 a.m. Instructor: Carl Newberg, MicroStat Laboratories, Dangelmayer Associates LLC This tutorial will cover the issues surrounding the causes, effects and solutions to electrostatic attraction in a variety of industries. Electrostatic attraction problems plague industries from photographic to medical and electronics. In the electronics industry alone, electrostatic attraction problems can be found in disk drive assembly, wafer fabrication and PC board assembly. The solutions to these problems can be found by applying a combination of the fundamentals of electrostatics and contamination control. Details on clean rooms, ionization, materials, prevention and control of static electricity with many realworld problems and the solutions to those problems will be presented and discussed. FC161: Perfect ESD Storm 10:30 a.m. - 12:00 p.m. Instructor: Ted Dangelmayer, Dangelmayer Associates LLC Learn how to prepare for the Perfect ESD Storm that is brewing in the electronics industry. The trend towards extensive use of ultra-sensitive components (Class 0) and the widespread lack of CDM (Charged Device Model) understanding are brewing the Perfect ESD Storm. It is no longer business as usual, and it can take up to two years to prepare. This tutorial is intended for professionals who have a basic understanding of ESD but are not fully aware of CDM control techniques or the industry trend toward extremely sensitive devices and the counter measures that are necessary. Learn the answers to your questions as well as these examples. Are you skeptical about this news of a Class 0 trend? Is it really happening? Is it likely to be a problem in your factory? How big a problem is CDM in manufacturing? What is different about CDM controls? How do I tailor Ansi/ESD S20.20 for CDM and Class 0? Join us for this highly interactive tutorial and learn why this is inevitable and how to prepare for it. DD201: ESD Protection and I/O Design 1:00 p.m. - 4:30 p.m. Instructor: Michael Stockinger, Freescale Semiconductor, Inc. This tutorial is intended to provide the attendees with the tools to take a device and circuit level understanding of ESD protection methods and implement them effectively in I/O designs for CMOS bulk technologies. Beginning with a review of common ESD protection strategies, this course will focus more directly on how to build ESDrobust I/O cells and how to integrate them on a full chip. The tutorial will cover various types of I/O pads including analog, RF and digital pads. Different types of ESD protection strategies and their usage in I/O pad cells will be described, for example rail clamp, self-contained, and SCR based protection schemes. This course will also discuss the decisions and challenges which ESD and I/O designers typically face when designing I/O pads. More complex ESD solutions will also be described such as stacked rail clamps, ghost rails, and protecting signals that can swing below ground or above the supply. Finally, this tutorial will touch on various supply schemes including multiple power domains and isolated grounding schemes. It will end with discussing pad ring construction aspects for both wire-bond and flip-chip packages. DD302: Troubleshooting On-Chip ESD Failures 1:00 p.m. - 4:30 p.m. Instructor: Warren Anderson, Synopsys Inc. Certification: DD Diagnosing and fixing on-chip ESD product qualification failures can often be one of the more challenging aspects of work in ESD. The pressure to quickly find and correct an HBM/MM/CDM failure in order to qualify a product often compounds the inherent difficulty of troubleshooting. Experience diagnosing failures, though not desirable from a product qualification standpoint, can greatly improve troubleshooting skills. This tutorial will build troubleshooting experience and skills by presenting case studies of actual on-chip HBM failures in a workshop format. The evidence for each case will be revealed and the failure analyzed in the same manner as an actual failure. Participants will be led through and allowed to analyze each failure case, interacting with the instructor to determine its root cause and a solution. This tutorial will identify common concepts, methods, and tools useful in failure diagnosis. Participants should be familiar with CMOS technology, on-chip ESD breakdown phenomena, standard ESD protection circuits, and the HBM test procedure. Participants should also be acquainted with basic CMOS circuit design, should be able to read circuit diagrams, and should have a basic understanding of the function of IO circuits. 14 Customized, full color tutorial notes will be provided to each tutorial registrant

15 NEW FC165: Novel Methods for Fixing ESD Issues in the Factory for Both Electronics & Explosive Products 1:00 p.m. - 4:30 p.m. Instructor: Jay Skolnik, Skolnik Technical Training This class will be a 3-hour tutorial on ESD control for explosives and other energetic materials, introducing the students to the differences of ESD damage of electronics versus energetics. It will discuss the various energy levels and types of discharges which can cause catastrophic or latent failures. Enlightening demonstrations and case histories will be included to illustrate practical, real-life situations of past ESD-induced failures of energetic components and methods to prevent them, as well as explanations of the use of ESD mitigation in the work environment. Upon tutorial completion, the students should be able to understand ESD and the prevention of ESD failures be applying the proper mitigation & control techniques, as well as safely work with explosive applications while ensuring human safety, preventing catastrophic health hazards, injuries, and severe damages. DD/FC122: Use of the Digital Sampling Oscilloscope for ESD Measurements 1:00 p.m. - 4:30 p.m. Instructor: Larry B. Levit, LBL Scientific The digital sampling oscilloscope (DSO) finds application in measuring waveforms that occur infrequently or only once. Its sophisticated calculation and display capabilities give it utility for factory ESD, as well as, its role in monitoring ESD immunity waveforms for both component and system level ESD. Understanding instrument performance issues is important for proper use. DSO bandwidth and the sampling rate are often used interchangeably, although they serve completely different purposes. The bandwidth, sampling rate and memory depth of the instrument must be specified for the intended application. DSOs also have display modes which can hide undersampling artifacts and lead to incorrect conclusions. Selecting the appropriate display algorithm is important for both cosmetic purposes and to achieve correct results from the instrument. Also important for the proper use of any oscilloscope are selection of the input impedance and the setup of the trigger. For a DSO, the pretrigger value must also be set. In some cases equivalent time sampling can be used but in most ESD measurements, single shot acquisition is required. Finally, for ESD applications on the factory floor, there are a variety of probes that are used. These include, wide bandwidth current probes, clamp on current probes, single ended and differential voltage probes, as well as, high frequency antennas. Calculations and ESD Scenarios Review for ESD Program Manager Exam Preparation (STUDY SESSION) 5:00 p.m. - 6:00 p.m. Stevan G. Hunter, ON Semiconductor Two 1-hour review sessions to brush up on ESD calculations and discuss some practical ESD scenarios, to help prepare for the ESD program manager exam at the conference. Homework problems will be provided following the first review session, with solutions and discussion in the second session. MONDAY SEPTEMBER 28 FC101: How To s of In-Plant ESD Auditing and Evaluation Measurements 8:30 a.m. - 4:30 p.m. Instructors: Ted Dangelmayer, Dangelmayer Associates LLC; Carl Newberg, MicroStat Laboratories, Dangelmayer Associates LLC Certification: PrM Compliance verification is one of the most important elements of ESD program management and there are many technical and administrative pitfalls that can be avoided. The attendee will learn not only how to make valid auditing measurements in accordance with ESD TR53 Compliance Verification of ESD Protective Equipment and Materials, but also how to recognize and avoid common pitfalls. Common instruments will be explained as well as the invalid test results that can result when they are used incorrectly. Advanced auditing techniques will also be covered that enable Class 0 devices to be handled successfully. There are many ways to administer effective Compliance Verification programs. Two successful examples will be presented that were developed independently by different companies. Hidden administrative pitfalls that often result in poor compliance will also be discussed. This tutorial will be highly interactive with live demonstrations, in-plant photographs, and compelling video clips. Students will be encouraged to ask questions and to participate in the discussions Customized, full color tutorial notes will be provided to each tutorial registrant 15

16 Tutorials DD/FC230: System Level ESD/EMI: Principles, Design Troubleshooting, and Demonstrations 8:30 a.m. - 12:00 p.m. Instructor: Douglas Smith, D.C. Smith Consultants This system level ESD tutorial will cover several facets of ESD as applied to electronic systems. Many of the principles and troubleshooting techniques will be demonstrated on real circuits for the students, with several new experiments added since previous years. War stories will also be used to illustrate points. The emphasis will be on making the experience both entertaining and informative for the students using an intuitive approach without heavy mathematics. Topics covered will include 1) Characteristics of ESD events; 2) ESD principles as applied to electronic systems; 3) Design troubleshooting techniques; 4) Unusual forms of ESD that have been the cause of field failures including internal chair discharges; 5) High-frequency measurement techniques; and 6) System design principles. It is recommended that those attending this tutorial section have at least one year of a college level electronics circuits course. Knowledge of common circuit analysis techniques will be assumed. FC361: Class 0A Devices & Boards - ESD Controls and Auditing Measurements 8:30 a.m. - 12:00 p.m. Instructor: Terry Welsher, Dangelmayer Associates LLC Advanced ESD Controls and Auditing Measurements for CDM & Class 0 (ultra-sensitive) devices and Circuit Boards are not well known and there are many technical and strategic pitfalls that must be avoided. Industry definitions (threshold levels) for Class 0 will be described and the history of their use will be reviewed. The Class 0 category is broken down into sub-categories of increasing risk. Students will learn how to make valid measurements, avoid common pitfalls, and how to use this data to successfully handle Class 0 sensitivities. Advanced measurements will be described including event detection and high speed current measurements. Students will learn when each measurement type is useful. Compelling case studies will illustrate these techniques and the success they produce. ESD Control procedures for Class 0 manufacturing require customization, attention to detail and a full understanding of the technology. Thus, each company will need to develop a Class 0 ESD subject matter expert (SME) to ensure the correct and cost effective counter measures are taken. SOPs (Special Operating Procedures) developed by SMEs will be discussed that have proven to virtually eliminate Class 0 failures. This tutorial will be highly interactive with live demonstrations, in-plant photographs, and video clips. Students will be encouraged to ask questions and actively participate in the discussions. References to technical literature on ultra-sensitive devices will be included. NEW FC362: Using Different Air Ionization Technologies and Measuring Process Effects 8:30 a.m. - 12:00 p.m. Instructor: Larry B. Levit, LBL Scientific Air Ionizers come in many types and technologies and are application dependent. Measuring beneficial effects of ionization technology upon a process is a big challenge to evaluate system usefulness. Different technologies and different ion generation methods are available and understanding when each should be used and how to evaluate their effectiveness is the cornerstone of this class. The course focuses on the specific cleanliness of each technology and delivery mechanisms for ions. Measuring ionizer performance is a basic tool but does not ensure the value of a static control action; several methods for measuring the process results will be presented. A procedure for microcontamination measurement and statistical analysis will be covered. In the case where electrostatic attraction is causing robotic alignment issues, success can be measured by reduction of voltage on wafers cassettes or robotic arms or the frequency of occurrence of unwanted wafer movements. This is a straightforward electrostatic measurement but it only indicates whether the ionizers are reducing electrostatic charge. The rate at which the effect is taking place is the parameter which is a measure of success. This class will explore these nuances. DD/FC221: Correlation of ESD Robustness and Handling Threats 8:30 a.m. - 12:00 p.m. Instructors: Wolfgang Stadler, Intel Mobile Communications; Reinhold Gaertner, Infineon Technologies Nearly all integrated circuits are stressed according to the classical device testing models Human Body Model (HBM) and the Charged Device Model (CDM) during qualification with a defined current pulse in order to guarantee safe handling in an electrostatic-protected area. In manufacturing environment, electrostatic voltages are measured on operators, devices, boards or systems. The tutorial will present examples for charging and discharging in typical manufacturing environment based on real world case studies and discuss the question how those real-world ESD events correlate to the threshold values obtained in device qualification tests. Field problems that cannot be reproduced by the classical device testing models and appropriate test methods conclude the tutorial. Understand the ideas of the basic ESD qualification models HBM, Machine Model (MM), and CDM. Learn typical failure modes and understand which waveform parameters of the models are decisive for the failure modes. Learn some basic measurement methodologies of charging/discharging in a manufacturing environment. Get familiar with the waveform of typical real-world ESD events and understand how to assess the waveform with respect to the device qualification tests. 16 Customized, full color tutorial notes will be provided to each tutorial registrant

17 DD204: ESD Design in HV Technologies 8:30 a.m. - 10:00 a.m. Instructor: Lorenzo Cerati, STMicroelectronics; Joost Willemen, Infineon Technologies This seminar gives an introduction to ESD design in high voltage technologies for integrated circuits with pin voltages from 12V upwards. After a short introduction of typical applications and requirements, an overview of different technologies and the typical device portfolios in these technologies will be given. Different ESD protection concepts are introduced, analyzing advantages and disadvantages of the various possible approaches to implement ESD networks (diodes, snapback devices, active clamps ). Finally, HV-technology and design related challenges regarding ESD protection are discussed, with a special focus on the formation on parasitic bipolar devices and their impact on the circuit s ESD performance. The attendee will gain a good basic knowledge of the main characteristics of HV technologies, the different ESD protection concepts and ESD protection challenges that are specific for HV technologies. This will be a help for understanding and further development of HV ESD protection. An extensive literature list is provided for further study of various subjects regarding HV ESD. DD381: Electronic Design Automation (EDA) Solutions for ESD 10:30 a.m. - 12:00 p.m. Instructor: Michael Khazhinsky, Silicon Laboratories, Inc., The verification of ESD protection networks in modern integrated circuits is a difficult challenge due to increasing design and process complexity, higher pin-counts and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another; across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves, may become damaged as a result of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a significant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the recently released ESDA Technical Report TR (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development. DD231: Integrated ESD Device and Board Level Design 1:00 p.m. - 4:30 p.m. Instructors: Harald Gossner, Intel Mobile Communications; David Pommerenke, University of Missouri-Rolla Efficient ESD design for system level ESD can only be achieved if board and device level protection circuitry coincide. The purpose of this tutorial is to develop an understanding of board/ic interaction under IEC testing conditions and to discuss useful design strategies supported by appropriate tools. This is meant to be beneficial both for ESD engineers of ICs and board designers responsible for EMC/ESD compliant design of the system. While it has clearly been pointed out that even elevated IC level HBM targets are insufficient for achieving the required IEC ESD level, more awareness has to be developed for the detailed turn-on and clamping behavior of IC level and board level ESD protection components. High current characterization of board protection and IO circuit by TLP is a first step. This enables the board designer to assess the behavior of IC pins and select appropriate board protection elements. The design optimization should be based on high current models of board components and IC IOs and the numerical simulation of the protection network under ESD conditions. Finally, various test methods are available to evaluate the efficiency of implemented protection on board level quantitatively. DD103: An Overview of Integrated Circuit ESD: The ESD Threat, Testing, Design Concepts, and Debugging 1:00 p.m. - 4:30 p.m. Instructor: Alan Righter, Analog Devices, Inc.; Warren Anderson, Synopsys Inc. Many Integrated Circuit (IC) designers do not have a working knowledge of ESD. This tutorial presents aspects of ESD that are relevant to IC designers and will enable them to improve their first time right ESD track record. This tutorial will also be useful for a wide range of specialists including layout designers, I/O designers, test engineers, failure analysis engineers, quality and reliability engineers, and architects as well as ESD design engineers just entering the field. The student will learn the fundamentals of ESD design, know the variables which affect ESD robustness, understand that ESD design needs to be addressed early in the design cycle and be better able to interact with ESD design specialists, understand ESD testing and interpret failure analysis data. Customized, full color tutorial notes will be provided to each tutorial registrant 17

18 Tutorials FC360: Electrical Overstress (EOS) in Manufacturing and Test 1:00 p.m. - 4:30 p.m. Instructor: Reinhold Gaertner, Infineon Technologies Electrical overstress (EOS) is a major cause of device failure in manufacturing and in the field. Despite this, there is relatively little information on the sources of EOS and on prevention practices, particularly for the factory. In this tutorial, the fundamentals of device overstress are reviewed. Relationships among device EOS stressing models, such as the Wunsch-Bell curve, are discussed. The causes of EOS and EOS-like events in manufacturing are described and categorized by source and by stress-type. The difficulties in distinguishing between power-induced EOS and high current ESD events such as charged-board events (CBE) and cable discharge events (CDE) are discussed. Case histories, including failure analysis and root cause determination, are presented and the few relevant industry specifications are reviewed. Revised FC261: Electrical Fields - Practical Considerations for the Factory 1:00 p.m. - 4:30 p.m. Instructor: David E. Swenson, Affinity Static Control LLC ANSI/ESD S20.20 recommends that process essential insulators with a measured electrical field strength of >2000 volts at 1 inch should be kept a minimum of 12 inches from ESD susceptible items. In addition, for close proximity or contact, the standard requires that insulators have an electric field of <125 volts at 1 inch. Just what are the practical considerations of this statement? What is the size of a charged object that imposes a risk? The goal of this tutorial is to show, by demonstration, the field strength and resulting induction ability from different sized objects. The audience should gain a practical perspective of size and distance as related to electrical fields and induction and be able to relate the information to their own factory situations. NEW DD240: ESD Device Qualification Testing 1:00 p.m. - 2:30 p.m. Instructors: Brett Carn, Wolfgang Stadler, Intel Mobile Communications This tutorial addresses the details of both Human Body Model (HBM) and Charged Device Model (CDM) qualification testing. This course will help in interpretation of the HBM joint standard JEDEC/ANSI/ESD JS including the following details: Waveform verification, understanding of Table 2A (minimum required set of pin combinations) and Table 2B (legacy pin combinations), pin categorization and pin grouping, I/O pin sampling, stress plans details including efficient testing (reduction in pin count) and some debugging options. In addition, this course will discuss CDM testing details regarding waveform verification, stress plans, peak current (Ipeak) variability and how does it affect the testing results, and debugging options as well as an overview on the new CDM joint standard JEDEC/ANSI/ESD JS DD213: ESD, EOS and Latch-up Failure Analysis for Designers 3:00 p.m. - 4:30 p.m. Instructor: Jim Vinson, Intersil Corporation This tutorial will introduce the student to the field of failure analysis as it is performed on ESD, EOS, and Latch-up failures. This tutorial is not trying to make the student into a Failure Analyst. This takes 3-5 years of mentoring to cultivate. The emphasis will be on understanding the diagnostic process and applying the correct set of tools to the failure with the ultimate goal of determining a corrective action to improve the product s robustness to these stresses. Examples will range from discrete clamp debug to FA on a complex circuit. FA combines the skill set of a detective, designer, and device physicist to understand what has happened to cause failure. TUESDAY SEPTEMBER 29 Calculations and ESD Scenarios Review for ESD Program Manager Exam Preparation (STUDY SESSION) 5:00 p.m. - 6:00 p.m. Stevan G. Hunter, ON Semiconductor Two 1-hour review sessions to brush up on ESD calculations and discuss some practical ESD scenarios, to help prepare for the ESD program manager exam at the conference. Homework problems will be provided following the first review session, with solutions and discussion in the second session. 18 Customized, full color tutorial notes will be provided to each tutorial registrant

19 THURSDAY OCTOBER 1 FC164: Costly Controversial ESD Myths 9:00 a.m. - 12:30 p.m. Instructor: Ted Dangelmayer, Dangelmayer Associates LLC There are a number of common misunderstandings and controversies about electrostatic discharge (ESD) program management that can have significant impact on the implementation and maintenance of the ESD program. These misunderstandings or myths result in unnecessary expenditures and/or result in a compromise of the program integrity. These myths and controversies, such as latency are often cited by skeptics not wanting to adhere to certain standard ESD procedures. As a consequence, it is important to identify and dispel the myths as well as to understand the potential impact of latent failures. This tutorial highlights 10 common myths and supporting success studies as well as a success study on latency. The myths and success studies presented here were chosen to provide real-world examples of how an ESD program can be strengthened by understanding the fallacy in each of the myths. This understanding will result in more reliable products that are also more cost competitive. Although not a myth, latency it is a significant reliability consideration that is surrounded with controversy. Some experts will argue that latency is virtually nonexistent and others will claim that it is the dominant failure mode. Reality lies somewhere in between. The Latency study cites irrefutable evidence of latent failures in alarming proportions that must be factored into ESD programs and product design. FC110: Cleanroom Considerations for the Program Manager 9:00 a.m. - 12:30 p.m. Instructor: Larry B. Levit, LBL Scientific Certification: PrM Cleanrooms and clean environments are enabling technologies required for the manufacture of many products that have exacting contamination control requirements in order to achieve defined yield and reliability targets. Clean manufacture is required in the semiconductor, hard disk drive, flat panel display, and pharmaceutical industries, to name a few. Requirements of cleanroom/clean environments and tooling therein result in low humidity levels, low surface contamination levels, use of processrequired insulators, and a lack of natural ions in the controlled environment. These factors can contribute to development of elevated static charge levels in close proximity to sensitive product, presenting both a contamination and electrostatic discharge exposure. This tutorial will provide a detailed review of the following concepts: Cleanroom/clean environment function Airborne particle classification standards Cleanroom compliance monitoring test methodologies Electrostatic attraction relation to airborne and surface contamination Electrostatic discharge concerns Cleanroom static charge generation challenges and control methodologies In addition, several case studies of static charge control issues in clean environments will be presented. FC210: ESD Standards Overview for the Program Manager 9:00 a.m. - 12:30 p.m. Instructor: David E. Swenson, Affinity Static Control LLC Certification: PrM, inarte The EOS/ESD Association s introduction of the Program Manager Certification curriculum has created a need to modify the Standards Tutorial that has been presented for a number of years, mainly to help individuals prepare for the inarte Engineering and Technician Exams. Currently, many of the ESDA Standards and Standard Test Methods are discussed in depth in the individual tutorials related to the specific subject matter. This Standards Tutorial provides an overview of all the Standards, grouped into common test types, based on measurement probe and test instruments. A common methodology is used in this tutorial to cover the requirements, applications and specifications for each Standard and Standard Test Method. DD117: TCAD Fundamentals 9:00 a.m. - 10:30 a.m. Instructor: Kai Esmark, Infineon Technologies TCAD (technology computer aided design) tools have become an indispensable utensil for the semiconductor industry. The possibilities to analyze, predict and optimize a certain semiconductor device behavior through modeling semiconductor fabrication (Process TCAD) and semiconductor device operation (Device TCAD) are countless. This includes the area for ESD and Latch-up development, as early access to fundamental device parameters under very high current density and high temperature transients is the key to overcome the conceptual problem of concurrent engineering for ESD engineers. This tutorial serves as a basic introduction into TCAD tool chain including process and device simulation as well as the creation and integration of compact models for mixed more simulation. Focus points are the capabilities but also limitations of these tools, like the requirements for a 2D/3D simulation approach and the validity of the models describing the fundamental physics, especially in the high temperature regime. DD112: Latch-up Fundamentals 9:00 a.m. - 10:30 a.m. Instructor: Steven H. Voldman, Dr. Steven H. Voldman, LLC Certification: DD Latch-up continues to be of interest today in advanced CMOS, mixed signal (MS) CMOS, RF CMOS, BiCMOS and smart power technologies. Those attending this course will understand the fundamentals of CMOS latch-up. The course will focus on theory, test structures, application, experimental results, simulation and CAD design systems. Those attending will also understand the impact of design, semiconductor process and circuits on CMOS latch-up. Customized, full color tutorial notes will be provided to each tutorial registrant 19

20 Tutorials DD319: Physical Process, Device, and Circuit Simulation (TCAD) Methodologies in Application to Industrial ESD Research and Design 11:00 a.m. - 12:30 p.m. Instructor: Vladislav Vashchenko, Maxim Integrated Over last two decades numerical simulation with commercially available Technology CAD (TCAD) tools has being widely applied across industry and research organizations to address ESD protection design challenges, ESD solutions development, test chip design and validation of the device, clamp circuits and application circuit blocks as well as interpretation of the Failure Analysis results. Corresponding significant and diverse material has been accumulated in the literature and unpublished industry practices. At the same time the best practices and methodologies were not adequately summarized to bring them to the broad audience in easily accessible and practically usable way. As a result, they are way underused today. The purpose of this tutorial is provide a comprehensive structured review of the published ESD TCAD results and construct a step-by-step approach to successful methodology and best practices application. The presented material achieves this goal in several steps: (i) by means of review and classification of the most relevant studies where the ESD problems which have been addressed through TCAD simulation; (ii) by derivation of a generic physical simulation workflow based upon either process simulation or parameterized device definition followed by device simulation and mixed-mode analysis in ESD time domain; (iii) by outlining and classification of the major application physical ESD problems which can be addressed through 2D or 3D TCAD analysis. The presentation material in the tutorial is supported by numerous easy-to-understand simulation examples. With fabless and fab-light trends dominating in the semiconductor industry in recent years, one of the main focus points of the tutorial is overcoming the requirements of well calibrated process simulation flow for successful application of the TCAD methodologies. This is done by demonstrating the classes of problems and solutions that can be addressed in this environment. Another focal point of this tutorial is to demonstrate the mixed-mode simulation approach capability including device and circuit parameterization and automation. The tutorial is not linked to any specific TCAD tool set and is equally useful to the users with experience using TCAD tools from any vendor or to the ESD engineers providing problem statement input for TCAD engineers. The material is presented using physical problem statements and solutions to illustrate the efficiency of methodology for ESD practitioners and device engineers. The material is presented hierarchically on the levels of ESD device physics, clamps and product circuit sub blocks including study of possible latch-up scenarios. DD222: Practical Aspects of Latch-Up for Low Voltage CMOS: Design Rules, Layout Floor Planning, and Test 11:00 a.m. - 12:30 p.m. Instructor: Scott Ruth, Freescale Semiconductor, Inc. The idea of this tutorial would be to tackle the practical aspects of designing and testing for latch-up robustness. From a design perspective, layout floor-planning, design rules, and EDA checks will be covered. From a test perspective, standard DC latch-up testing as well as transient latch-up testing (including system-level ESD, cable discharge, and the evolving transient latch-up standard) will be covered. Finally, real world latch-up failures and diagnoses will be presented. DD220: Transmission Line Pulse (TLP) Basics and Applications 1:30 p.m. - 5:00 p.m. Instructors: Evan Grund, Grund Technical Solutions; Robert Ashton, ON Semiconductor Certification: DD This tutorial will cover the basics of TLP including underlying theory, the types of TLP systems available and how I-V curves are extracted from TLP pulses. The tutorial uses examples to show how fundamental device parameters can be measured with TLP. These parameters allow the ESD engineer to understand a technology s properties which can be used to design successful ESD protection circuits. The student will gain an understanding of the purpose of TLP measurements, how TLP relates to HBM and CDM, fundamentals of how TLP systems work including impedance and reflections, types of TLP systems, importance of load lines, adaptive ranging, TLP calibration, time dependence from TLP, and biased TLP measurements. The tutorial will present examples of TLP use for nmos transistors, diodes, oxides/capacitors, power supply clamps, as well as time dependent TDR-O and VF-TLP examples. 20 Customized, full color tutorial notes will be provided to each tutorial registrant

21 DD301: SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits 1:30 p.m. - 5:00 p.m. Instructor: Christian Russ, Intel Mobile Communications Certification: DD I/O ESD protection networks comprising dual diodes to the power/ground rails and networks of RC triggered active MOSFET rail clamp circuits have become prevalent in the industry for low voltage CMOS (<5 volt) process technologies. These networks have become popular because they offer clear advantages over prior ESD solutions in terms of fab portability, scalability, layout area, and ease of compact modeling for circuit simulations in SPICE. In this tutorial, we will explore in turn each of the key elements in active ESD networks including diodes, active clamp devices, and trigger circuits. We will cover in detail the important role that power rail resistance plays in determining the optimum size and placement of clamps in a protected bank of I/Os. We will review approaches for ESD-hardening of I/Os with more robust output driver configurations and secondary input protection circuits. Next, a step-by-step methodology for SPICE-based ESD network design and optimization will be introduced. Examples of this design methodology will be shown for both a kit-based and full-custom design approach. Finally, depending on time available, we will review a range of special topics including advantages in using isolated PWELL in ESD designs, HV and HV-tolerant network designs, and ESD networks for SOI technologies. FC201: ESD - A Surprisingly Frequent Root Cause of Device Failure 1:30 p.m. - 5:00 p.m. Instructor: Ted Dangelmayer, Dangelmayer Associates LLC While most companies are acutely aware of the hazards of ESD, few are aware of just how pervasive ESD failures actually are. Likewise, many ESD Program Managers have difficulty securing adequate management support. This tutorial will shed light on multiple sources of ESD damage and the circumstances where ESD failures dominate. Recent studies into the misdiagnosis of EOS failures suggest that ESD damage may, in fact, occur much more often than previously realized especially at the circuit board level. This fact is a compelling justification for strong management support. The student will also learn which are the most frequent ESD failure mechanisms among CDM, HBM and MM and why. The student will also learn about the best practices for prevention for these recently recognized sources of ESD damage. DD380/FC380: Electrostatic Calculations for the Program Manager and the ESD Engineer 1:30 p.m. - 5:00 p.m. Instructor: Leo G. Henry, ESD/TLP Consultants, LLC Certification: PrM, inarte This tutorial focuses on the basic calculations and techniques of use to the program manager and the ESD engineer. The content is at the introductory college pre-calculus and introductory college physics level set in the context of electrostatic discharge and its effects. It is suggested that the student gain some familiarity with these subjects prior to the tutorial. Topics covered include the electric force, the electric field and Coulombs law, electric potential, and voltage. Gauss Law is discussed as it relates to the electric field, induction, and the Faraday cup. The capacitance in Q = CV is used to explain charge sharing. RC decay is discussed as it relates to ESD discharge from humans, devices, wrist straps, and materials. After completing this course, the attendee should leave with a proper understanding of the differences among the calculations for peak current, power, energy, and threshold voltage for a simple device. FC200: Packaging Principles for the Program Manager 1:30 p.m. - 5:00 p.m. Instructor: David E. Swenson, Affinity Static Control LLC Certification: PrM Shipping electronic parts within a factory, to another factory, distributor, or to an end-user has always been an area of uncertainty within the manufacturing process. To provide clear-cut information on what type of controlled packaging should be used in any situation, the EOS/ESD Association, Inc. released a comprehensive revision of the obsolete industry standard EIA The newer document, ANSI/ESD S541, is the focus of this inclusive session. It provides information and guidance, as well as material specifications, to assist in the design and implementation of a packaging plan for use within an ANSI/ESD S20.20 based ESD Control Program. Current and newly released test method standards suitable for packaging material evaluation will be described. Course credit applies to the ESD Program Manager Certification curriculum. Previous attendance at the ESD Basics and How To s tutorials are highly recommended. Customized, full color tutorial notes will be provided to each tutorial registrant 21

22 Technical Sessions Recordings of Technical Sessions: 1A, 1B, 2A, 2B, 3A, and 3B are available for purchase. Symposium attendees, University professionals, or students can purchase the recorded sessions for $50. Please see registration form for ordering. Tuesday September 29 th Parallel Sessions Exhibitor Showcase: 10:10 AM-10:20 AM Barth Electronics Session 1A 10:20 AM-12:00 PM 1A: ESD Protection in Advanced Technologies Moderator: Gene Worley, Qualcomm, Inc. 1A.1 Innovative High Density ESD Protection Device in State of the Art FDSOI UTBB Technologies Pascal Fonteneau, Yohann Solaro, David Marin-Cudraz, STMicroelectronics; Claire Fenouillet-Beranger, CEA-LETI MINATEC For the first time, we demonstrate an innovative way to build ESD protection in FDSOI technologies. This protection is compounded of two stacked devices one on the other: a bottom bulk-thyristor and a top thin film triggering device. Low leakage current, tunable triggering voltage and high current capability are highlighted. 1A.2 Design and Optimization of ESD Lateral NPN Device in 14nm FinFET SOI CMOS Technology You Li, Rahul Mishra, Liyang Song, Robert Gauthier, IBM We presented the development of ESD lateral NPN device in 14nm FinFET SOI CMOS technology by using bodycontact and floating-body approaches. The effects of key design factors including base length, base doping, body resistance on the triggering and ESD performance of LNPN device are investigated to achieve an optimized design. 1A.3 VFTLP Characteristics of ESD Protection Diodes in Advanced Bulk FinFET Technology Shih-Hung Chen, Dimitri Linten, Mirko Scholz, Geert Hellings, Aaron Thean, imec; Roman Boschke, Guido Groeseneken, Katholieke Universiteit Leuven Beyond 20nm nodes, bulk FinFET is the mainstream technology; however, new process options can result in significant impacts on intrinsic ESD performance. In this work, we study on vftlp characteristics of two types of ESD diodes. The corresponding TCAD simulations bring an in-depth understanding on the physical mechanism of these ESD diodes. 1A.4 ESD Characterization of Germanium FinFET Diodes and ggmos Roman Boschke, Guido Groeseneken, imec, Katholieke Universiteit Leuven; Geert Hellings, Dimitri Linten, Mirko Scholz, Shih-Hung Chen, Jerome Mitard, Liesbeth Witters, imec Germanium as a high mobility material is a candidate to replace Silicon as channel material for future scaled FinFETs. This work presents the ESD robustness of gated diodes and ggmos in Ge FinFETs. Strained Germanium ggpmos shows 3x lower failure current compared to relaxed Ge, because of heterostructure confinement effect. Exhibitor Showcase: 10:10 AM-10:20 AM Lubrizol Conductive Polymers Session 1B 10:20 AM-12:00 PM 1B: Factory Control I Moderator: Wolfgang Stadler, Intel Mobile Communications RCJ: Development of a Perfectly Balanced Electrostatic Eliminator Utilizing an Intermittent Pulse AC Voltage Power Supply RCJ Invited Paper Katsuyuki Takahashi, Akira Goto, Shinichi Yamaguchi, Tomokatsu Saito, Kensuke Sakamoto, Hidemi Nagata, Shishido Electrostatic A perfectly balanced fan type electrostatic eliminator utilizing an intermittent pulse AC voltage power supply is developed. The short-term fluctuation range of the offset voltage (ion balance) is smaller than ±2 V without a sensor feedback system. The high performance is maintained in 2500 h continuous operation. 1B.1 Analysis of Pulsed DC Ionizer Measurement Procedures with a CPM Using ESDA RP Lawrence Levit, LBL Scientific; William Vosteen, Monroe Electronics; Geoffrey Weil, Anodyne Research Ionizer measurement with a charge plate monitor utilizes ANSI/ESD STM for adjusting an ionizer. This method measures the maximum offset voltages which are known to fluctuate considerably. In this work, the procedure is simulated with SPICE. The fluctuations were observed and explained. A procedural change is recommended which has been shown to make the measurement stable and repeatable. 1B.2 Manufacturing Changes Air Ionization Technology Arnold Steinman, Electronics Workshop, Dangelmayer Associates LLC Manufacturing has brought increased semiconductor device functionality through smaller geometries, larger wafer sizes, and faster operating speeds, as well as increased disk drive storage density and display sizes. To produce these advanced technologies the use of air ionization for static control has changed. This paper explores new ionization requirements and methods. 1B.3 A Novel New Concept in Hybrid Alpha Ionization Systems Lawrence Levit, LBL Scientific; Geoffrey Weil, Anodyne Research A novel ionizer based upon a hybrid alpha and pulsed high voltage bias ionizer is presented. It Places the ionizer in the process chamber and biases it remotely through a plastic window using only fields. It performs very nearly identically to such an ioniz4er with hard wiring to the source. Because the circuit is a capacitor, the ionizer is automatically balanced with no need to adjust the balance. 22

23 Tuesday September 29 th Parallel Sessions Exhibitor Showcase: 1:00 PM-1:10 PM ESDEMC Technology, Inc. Session 2A 1:10 PM-2:50 PM 2A: ESD Design in RF and Power Devices Moderator: Christian Russ, Intel Mobile Communications 2A.1 An Electrostatic-Discharge-Protection Solution for Silicon-Carbide MESFET T. Phulpin, D. Tre mouilles, K. Isoird, P. Austin, LAAS/CNRS, Universite de Toulouse; D. Tournier, Universite de Lyon; P. Godignon, Universitat Auto noma de Barcelona Among wide band gap material for power electronic, Silicon Carbide (SiC) is the most advanced and starts to gain market shares. We have studied SiC MESFET ESD robustness. To solve the problem of their low intrinsic ESD robustness, we demonstrate in this work an effective protection solution and possible improvements. 2A.2 Self-ESD-Protected Transmission Line Broadband in CMOS28nm UTBB-FDSOI Johan Bourgeat, Boris Heitz, Jean Jimenez, Philippe Galy, STMicroelectronics; Tekfouy Lim, EMFT Advanced CMOS technologies, and particular Ultra-Thin Body and BOX Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology provide good performances for analog high frequency and ultra-low power applications. We present in this paper self- ESD-protected transmission lines based on two different ESD strategies. Specific ESD protections based on bidirectional SCR (bi-scr) are directly embedded on the transmission line. 2A.3 CDM-Reliable T-coil Techniques for High-Speed Wireline Receivers Min-Sun Keel, Elyse Rosenbaum, University of Illinois at Urbana-Champaign Inherent CDM hazard of a T-coil from magnetic coupling is analyzed, and a proposed inductance halving technique can reduce magnetic coupling during ESD. From simulation, the proposed T-coil can effectively suppress voltage overshoot and minimize bandwidth degradation, compared to the conventional secondary ESD protection. 2A.4 Robust ESD Clamp for Envelop Tracking Power Supply Iqbal Chaudhry, Nathaniel Peachey, Qorvo An ESD clamp intended for Envelop Tracking applications is presented. The clamp uses a reliable trigger mechanism to turn the clamp on during an ESD event. Important clamp features are immunity to voltage spikes in the power supply and a reliable power up operation. The clamp design has been validated with experimental data. Exhibitor Showcase: 1:00 PM-1:10 PM Megalin Source International Co., Ltd. Session 2B 1:10 PM-2:50 PM 2B: System Level ESD Design Moderator: Fabrice Caignet, LAAS/CNRS 2B.1 Practical Methodology for Extraction of SEED Models Collin Reiman, Nicholas Thomson, Yang Xiu, Robert Mertens, Elyse Rosenbaum, University of Illinois at Urbana-Champaign A custom test board facilitates TLP characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin-level response of the IC to an IEC discharge. ESD gun zaps are applied to the test board; simulated and measured waveforms are compared. 2B.2 ESD Induced Functional Upset in Magnetic Sensor ICs Donald Dibra, Kai Esmark, Stefan Jahn, Mario Motz, Infineon Technologies This paper discusses the functional upset behavior of magnetic sensor ICs for automotive applications during ESD system level tests according to the ISO standard. The system level ESD functional upset robustness is presented for two different sensors, one with and one without a supply voltage drop capability (μ-cut functionality). 2B.3 Secondary Discharge A Potential Risk during System Level HBM ESD Testing Heinrich Wolf, Horst Gieser, Fraunhofer EMFT By means of a floating handheld electronic system this paper describes the influence of secondary discharge events during system level ESD testing on the failure threshold of the involved electronic circuit. In order to increase the robustness it was necessary to determine the discharge current target levels followed by an optimization of the board layout. 2B.4 A Passive Coupling Circuit for Injecting TLP-Like Stress Pulses into only one End of a Driver/Receiver System Benjamin Orr, Missouri University of Science and Technology, Intel Mobile Communications; David Johnsson, Krzysztof Domanski, Harald Gossner, Intel Mobile Communications; David Pommerenke, Missouri University of Science and Technology In this paper, a simple passive circuit is presented which allows TLP stress and characterization pulses to be injected into only one side of a driver/receiver system. The circuit is simulated and tested, demonstrating the possibility for directional current injection on the order of 60:1. The circuit also provides a method for measuring both injected currents when paired with a typical TLP system. 23

24 Technical Sessions Tuesday September 29 th Parallel Sessions Session 3A 3:45 PM-5:00 PM 3A: ESD Checking and Verification Moderator: Robert Gauthier, IBM Corporation 3A.1 Essential Integration of ESD Verification Methodologies N. Trivedi, D. Alvarez, Infineon Technologies Integrating DRC-like and Topology checks and in addition, incorporation of clamp resistance from Interconnect checks during ESD verification of SoC is presented. The benefit of integrating these three static methodologies together is shown by the detection of new critical constructions and the automatic waiving of uncritical ones. 3A.2 Schematic-Level and Layout-Level ESD EDA Check Methodology Applied to Smart Power IC s Initialization and Implementation Eleonora Gevinti, Lorenzo Cerati, Leonardo Di Biccari, Giuseppe Ballarin, Antonio Andreini, Mauro Fragnoli, Antonio Bogani, STMicroelectronics A functional methodology to fully check IC ESD network topology together with protected circuitry ESD compliance at Schematic-Level and metal interconnections at Layout-Level is developed and applied to Smart Power products. A common operational method is ideated to simultaneously initialize different Schematic-Level and Layout-Level verification tools. 3A.3 A Comprehensive ESD Verification Flow at Transistor Level for Large SoC Designs Je ro me Lescot, Patrice Dehan, Wahbi Boujarra, STMicroelectronics; Dina Medhat, Sophie Billy, Mentor Graphics A fast yet robust multi-domain ESD verification flow at transistor level has been developed for large SoC designs. All steps of the verification process from initial power domains configuration to the final debugging process are covered in this comprehensive solution that supports scalable ESD protection structures. Session 3B 3:45 PM-5:00 PM 3B: ESD Failure Case Study Moderator: Scott Ruth, Freescale Semiconductor, Inc. 3B.1 HBM Failures Induced by Circuit Interaction with ESD Cell Behavior Yang Xiao, Ann Concannon, Rajkumar Sankaralingam, Texas Instruments Circuit topology based ESD checks lead to inadequate HBM performance due to transient circuit interaction with ESD cell behavior. The HBM failures were narrowed down to circuit interaction at ESD cell turn-on and turnoff. 3B.2 Soft Fails Due to LU Stress of Virtual Power Domains Krzysztof Domanski, Harald Gossner, Intel Mobile Communications A shut-down of IC was caused by current injection into a USB 2.0 pin. Root cause was a substrate current forced into a power rail supplied by a weak LDO. Connecting the guard rings to a robust VDD supply resolved the problem. As the failure could not be revealed by JESD78 testing, a modified Latchup test setup is proposed. 3B.3 ESD Failure Caused by Parasitic SCR in an Overvoltage Tolerant I/O D. Alvarez, M. Wendel, A. Stuffer, Infineon Technologies A new type of ESD failure in an overvoltage tolerant I/O of a CMOS embedded flash technology is presented. The failure is caused by the triggering of a parasitic SCR formed by high voltage devices between I/O and supply. Several solutions to prevent the failure are shown. 24

25 Wednesday September 30 th Parallel Sessions Industry Council Update 8:00 a.m. - 8:10 a.m. Charvaka Duvvury, ESD Consulting LLC Year in Review: The Continued Evolution of CDM in Manufacturing, Design, Modeling, and Testing Standards 8:10 a.m. - 8:50 a.m. Alan Righter, Analog Devices, Inc. As the primary real-world model for manufacturing / automated handling ESD, Charged Device Model (CDM) has seen much advancement both within our EOS/ESD Association, Inc. and around the electronics industry as well. This Year-In-Review will summarize the key CDM developments in several areas, along with a first focus on industry trends and how they affect CDM. A new joint CDM Standard (ANSI/ESDA/JEDEC JS-002) has been completed, featuring a number of improvements from previous standards in terms of platform, measurement, and verification, promising to serve as a catalyst for world-wide harmonization of CDM testing. A number of key CDM-related research topics from recent papers within our Symposium as well as in outside publications (covering manufacturing / handling related CDM issues, CDM design, CDM modeling and technology aspects) will also be featured and reviewed in this talk. Exhibitor Showcase: 9:00 AM-9:10 AM RTP Company Session 4A 9:10 AM-10:25 AM 4A: TCAD Design and Simulation Moderator: Vladislav Vashchenko, Maxim Integrated Exhibitor Showcase: 9:00 AM-9:10 AM NRD Advanced Static Control Session 4B 9:10 AM-10:25 AM 4B: Tester and Testing Method I Moderator: Mike Chaine, Micron Technology, Inc. 4A.1 A Study of the Effect of Remote CDM Clamps in Integrated Circuits Dolphin Abessolo-Bidzo, Theo Smedes, NXP Semiconductors; Peter C. de Jong, Synopsys, Inc. Cross-domain signals are the largest ESD risk in integrated circuits nowadays. In this paper a study of the effect of remote CDM clamps in IC s is presented. Predictive ESD simulations are demonstrated by TLP and vf-tlp characterizations and by means of HBM and CDM qualifications of a dedicated ESD testchip. 4A.2 An Off-Chip ESD Protection for High-Speed Interfaces Guido Notermans, Hans-Martin Ritter, Joachim Utzig, Steffen Holland, Zhihao Pan, Jochen Wynants, Paul Huiskamp, Wim Peters, Burkhard Laue, NXP Semiconductors High-speed interfaces, e.g. for USB3.1 or HDMI2.0, require high system level ESD protection, typically 15 kv, without affecting signal integrity. This paper describes the development of a novel bipolar process and the design of a fast-switching, low-voltage clamping protection combining high protection capability with excellent signal integrity. 4A.3 Active Clamps with Hybrid BJT-CMOS Operation Mode Vladislav Vashchenko, Blerina Aliaj, Augusto Tazzoli, Maxim Integrated Corp.; Andrei Shibkov, Angstrom Design Automation A method to exploit the internal gain of the parasitic bipolar transistor in integrated LDMOS devices achieving a mixed bipolar-cmos regime is proposed and validated using numerical simulation and experimental results. An improvement and surge operation regime is demonstrated. 4B.1 TLP-Based Human Metal Model Stress Generator Re mi Be ges, Freescale Semiconductor, Inc., LAAS/CNRS; Fabrice Caignet, Nicolas Nolhier, LAAS/CNRS, Univ. de Toulouse; Patrice Besse, Jean-Philippe Laine, Alain Salles, Freescale Semiconductor, Inc; Nicolas Mauran, Marise Bafleur, LAAS/CNRS A new setup for generating a Human Metal Model compliant waveform with a TLP is described. The computation of the generator output impedance in the time domain allows to quantify differences of this setup versus TLP and HMM. It provides interesting information to understand the recurrent lack of correlation between TLP and HMM tests. 4B.2 ESD Protection of Open-Drain I2C using Fragile Devices in Embedded Systems Farzan Farbiz, Muhammad Y. Ali, Raj Sankaralingam,Texas Instruments Design guidelines are presented to achieve efficient ESD protection on open-drain outputs. We will show that standard characterization techniques may lead to an inaccurate estimate for the device failure current and hence oversizing the output transistor. A design framework for I2C output stage based on a new characterization technique is presented to minimize the cost of ESD protection. 4B.3 Using CC-TLP to get a CDM Robustness Value Kai Esmark, Reinhold Gaertner, Stefan Seidl, Friedrich zur Nieden, Infineon Technologies; Heinrich Wolf, Horst Gieser, Fraunhofer EMFT CDM-like stress represents the highest ESD risk during handling of single devices. Today CDM-tests can only be performed on packaged products on not very reliably test equipment using an air discharge. The paper shows how Capacitively Coupled TLP (CC-TLP) can be used to apply a CDM- like stress to the device even on wafer level. Data will be shown to compare the stress individual failing level and the failure locations on the chip. 25

26 Technical Sessions Wednesday September 30 th Parallel Sessions Session 5A 11:20 AM-12:10 PM 5A: 3D Chip Stacking ESD Protection Moderator: Charles Chu, Maxim Integrated 5A.1 ESD Protection Design in Active-Lite Interposer for 2.5 and 3D Systems-in-Package Mirko Scholz, Geert Hellings, Shih-Hung Chen, Dimitri Linten, Mikael Detalle,Cesar Roda Neve, Antonio La Manna, Geert van der Plas, Eric Beyne, imec Adding a few front-end of line masks to a passive interposer technology enables the low-cost processing of diodes, SCRs and bipolar transistors. Using those devices in an ESD protection design allows moving a large part of the ESD protection from the stacked die to the interposer. 5A.2 3D Integration ESD Protection Design and Analysis Souvick Mitra, Ephrem Gebreselasie, You Li, Robert Gauthier, Joel Silberman, Christy Tyberg, Katsuyuki Sakuma, Thuy Tran-Quinn, Koushik Ramachandran, Matthew Angyal, IBM Corporation Design of Experiments (DOEs) was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection. Session 5B 11:20 AM-12:10 PM 5B: Factory Control II Moderator: John Kinnear. IBM 5B.1 Multi-Physics Simulations for Triboelectric Charging of Display Panels during Roller Transfer Process Ki-Hyuk Kim, Missouri University of Science and Technology, Samsung; David Pommerenke, Yingjie Gan, Missouri University of Science and Technology A multi-physics simulation methodology for the tribocharging during the roller transfer process of display panels is proposed. Electrical and mechanical models for the triboelectric charging are developed and simulation results for the transient triboelectric charges and the E-field distribution of the display panel with insulating and dissipative rollers are presented. 5B.2 ESD Failure and Disturbance Cases in Electrostatic Protective Areas Pasi Tamminen, Leena Ukkonen, Lauri Syda nheimo, Tampere University of Technology; Toni Viheria koski, Cascade Metrology Electrostatic protective area (EPA) can effectively prevent ESD failures from charged operators, equipment and packages. However, electrical disturbances and ESD events can still exist in well build EPAs. In this paper failure cases found in electronic assembly environment are analyzed based on the source, event type and failure information. 26

27 Wednesday September 30 th Parallel Sessions Session 6A 1:20 PM-3:00 PM 6A: ESD Simuation and Verification Moderator: Eleonora Gevinti, STMicroelectronics Session 6B 1:20 PM-3:00 PM 6B: Factory Control III Moderator: Reinhold Gaertner, Infineon Technologies 6A.1 A Full-Chip ESD Simulation Flow Steven S. Poon, Kushal Sreedhar, Chinmay Joshi, Intel An ESD simulation flow that has been demonstrated on 14 nm products is described. Due to Moore s Law, ESD protection devices are having an increasingly large impact on silicon area, power, and capacitance. A number of real-world examples demonstrating how the simulation flow improved these areas are provided. 6A.2 A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures Melanie Etherton, Scott Ruth, Jim W. Miller, Rishabh Agarwal, Rishi Bhooshan, Freescale Semiconductor; Maxim Ershov, Meruzhan Cadjan, Yuri Feinberg, Silicon Frontline Technology Inc.; Karthik Srinivasan, Norman Chang, Youlin Liao, Apache Design, Inc. This abstract describes a new full-chip CDM ESD verification method that enables the evaluation of complete integrated circuits for CDM risk. We demonstrate that a robust analysis must comprehend millions of locations of driver-receiver (D/R) pairs on an IC, an accurate model of the grid resistance and an adequate representation of the current distribution. 6A.3 Fast Circuit Simulator for Transient Analysis of CDM ESD Kuo-Hsuan Meng, Elyse Rosenbaum, University of Illinois at Urbana-Champaign Run-time for circuit-level CDM ESD simulation can be prohibitively long; by leveraging the specific properties of the problem formulation, run-time can be reduced without compromising accuracy. A reduced run-time is obtained using cluster computing, and nearly 30X additional speed-up is achieved using specialized device models and a customized simulator. 6A.4 P2P and RMAP - New Software Tool for Quick and Easy Verification of Power Nets Maxim Ershov, Meruzhan Cadjan, Yuri Feinberg, Silicon Frontline Technology; Thomas Jochum, Intersil; Scott Ruth, Melanie Etherton, Freescale Semiconductor, Inc. A new software tool, P2P, for electrical simulation of power nets is presented. Rmap functionality of P2P calculates resistances from specified points to all points on the net, and visualizes resistance color maps which enables quick identification and debugging of layout errors. P2P also enables point-to-point resistance calculation, IR voltage drop analysis, and current density verification. 6B.1 Benchmarking of Factory Level ESD Control Toni Viheriaekoski, Cascade Metrology; Jari Kohtama ki, ABB Oy; Terttu Peltoniemi, Nokia; Pasi Tamminen, Microsoft A standard compliance of the factory level ESD control varies between organizations. We have audited twelve different factories during the 24-month benchmarking period. These audits were focused on the ESD control programs and the process control. Summary of the results and examples of the best practices are presented in this paper. 6B.2 How Six Sigma brought over 1 million $ saving and improved manufacturing process by 98.9% at Nexteer Automotive Kamil Drab, Mariusz Kwiatkowski, Philip Wasalaski, Nexteer Automotive Using Six Sigma Methodology along with 3M EM Eye ESD Event Detector device Nexteer Automotive reduced the level of ESD events by 98.9% in area of Electronic Assembly Line. These activities brought savings over 1 million dollars in Production Process and EOM customer satisfaction. 6B.3 Uncertainties in Charge Measurements of ESD Risk Assessment Toni Viheriaekoski, Cascade Metrology; Jari Kohtama ki, ABB Oy; Terttu Peltoniemi, Nokia; Pasi Tamminen, Microsoft Charge measurement techniques are often considered too complicate to the process control of electronics manufacturing. In his study, we show that expensive instrumentation is not necessarily needed for characterizing electrostatic source circuit parameters in a risk assessment. Measurement can be made accurately when uncertainties are properly taken into account. 6B.4 Probabilistic Analytical Benchmarking for ESD Manufacturing Process L. H. Koh, Y. H. Goh, Everfeed Technology Pte, Ltd.; C. B. Goh, Panasonic Industrial Devices A chronological ESD process analysis is proposed to identify the root cause of ESD sensitive devices premature failure due to several field returns from customers exceeding factory targeted ESD failure control threshold. Two novel quantitative ESD risk indices area proposed to benchmark the process ESD capability using probabilistic statistical technique. 27

28 Technical Sessions Wednesday September 30 th Parallel Sessions Session 7A 3:20 PM-5:00 PM 7A: HV ESD Clamp Design Moderator: Mototsugu Okushima, Renasas 7A.1 Design and Optimization on ESD Self-Protection Schemes for 700V LDMOS in High Voltage Power IC Zhong Chen, Akram Salman, Guru Mathur, Gianluca Boselli,Texas Instruments, Inc. This paper presents an ESD self-protection scheme for a 700V high-voltage laterally diffused metal-oxidesemiconductor (LDMOS) field effect transistor. The safe operating area (SOA) and breakdown failure mechanism of 700V LDMOS are discussed by simulations and experimental results. The scalability of thermal failure current with LDMOS width is also demonstrated. 7A.2 Engineering of Dual Direction SCR Cells for Component and System Level ESD, Surge, and Longer EOS Events Augusto Tazzoli, Vladislav Vashchenko, Maxim Integrated Corp. Bidirectional SCRs were developed and experimentally validated as a viable solution to protect against component and system level ESD events, surge transients, and even longer EOS stresses. Engineering of both device front- and back-end allowed obtaining low leakage and capacitance, and a linear scalability of passing level upon device width. 7A.3 Investigation and Solution to the Early Failure of Parasitic NPN Triggered by the Adjacent PNP ESD Clamps Ming-Fu Tsai, Jen-Chou Tseng, Kuo-Ji Chen, Ming- Hsiang Song, TSMC The mechanism of PNP-triggered parasitic NPN s early failure during ESD stress has been clarified for the first time. We proposed two solutions for the high ESD and Latchup-hard requirements. The embedded SCR structure provides high HBM immunity, which can serve pin-to-pin protection such as the differential IO application. For the Latchup-hard solution, a sandwich guard ring structure solves the snapback-induced local ESD damage issue and achieves low substrate current injection. Note that the spacing rule for the parasitic NPN structures is also greatly reduced up to 44.7%. 7A.4 Active Clamp Design for On-Chip GUN Protection Andreas Rupp, Ulrich Glaser, Yiqun Cao, Infineon Technologies On-chip active clamps show attractive performance for the component-level ESD protection like HBM, but suffer usually from their weakness for short-pulse and high-current events like the first peak of IEC (GUN) pulses. By adequate active clamp design this disadvantage can be overcome, resulting in an area efficient active clamp GUN protection. Session 7B 3:20 PM-5:00 PM 7B: System Level ESD Testing Moderator: Harald Gossner, Intel Mobile Communications 7B.1 Air-Discharge Testing of Single Components Hans-Martin Ritter, Lars Koch, Mark Schneider, Guido Notermans, NXP Semiconductors A test set-up for an air discharge on single components has been investigated. Excellent repeatability can be achieved with an optimized set-up. First peak of pulse is missing due to long risetimes. Surprisingly, the total charge in an air discharge pulse is larger than in a contact discharge. 7B.2 The Effect of USB Ground Wire and Product Dynamic Capacitance on IEC Qualification Pasi Tamminen, Leena Ukkonen, Lauri Syda nheimo, Tampere University of Technology IEC discharge stress levels are studied with varying product capacitance and ground connections. Stress levels are evaluated based on the measured and simulated peak current, peak power, pulse rise time, and energy transfer along to the USB wire. These stress parameters can be significantly affected by adjusting the test setup. 7B.3 Versatile Models and Expanded Application of the IEC Test Timothy J. Maloney, Intel Corporation An all-purpose circuit model and associated shorting current waveform expression for the IEC pulse is presented. Criteria include agreement with existing IEC guidance plus zero field derivative at t=0, for accurate radiation modeling. Also, a capacitive coupling tool for IEC pulsers is used to simulate platform I/O port hazards. 7B.4 S-Parameter Based Modeling of System-Level ESD Test Bed Yang Xiu, Nicholas Thomson, Robert Mertens, Elyse Rosenbaum, University of Illinois at Urbana-Champaign The IEC test bed is modeled with circuit elements extracted from S-parameter measurements. Simulated current waveforms are consistent with measurement for both a tethered and a floating system without customizing the model parameters for each case. 28

29 Thursday October 1 st Year in Review: Understanding EOS in Automotive Industry 8:00 a.m. - 8:40 a.m. Christoph Thienel, AE/EIQ, Robert Bosch GmbH, The automotive industry requires 100% safe and reliable components. Today, customer returns of automotive IC components due to Electrical Overstress (EOS) are still common. EOS damages caused by ESD in the field are rare due to appropriate on-chip and board-level protection. However, EOS damages are not caused by a component weakness, but rather by incorrect operation of the components on the side of the OEM. Coupling of high inductive voltages or hot-plugging of boards and devices during assembly or service are leading causes of component EOS. Customers often don t know which action caused the electrical overstress on the board or component and request solutions from suppliers to avoid future damaged parts. In some cases, it is incorrectly assumed that higher component ESD robustness can prevent EOS issues driving requests for higher ESD qualification levels. This presentation will demonstrate a simple and consistent description of EOS that guides more customer awareness of causes and preventative measures. Example ideas and activities that have been developed to help guide automotive customers to avoid EOS damages will be presented. Session 8A 8:50 AM-10:30 AM 8A: Tester and Testing Method II Moderator: Heinrich Wolf, Fraunhofer EMFT 8A.1 Wear out Effects in ESD Characterization and Testing T. Smedes, D. Abessolo-Bidzo, NXP Semiconductors Wear out effects of multiple stresses may have significant impact on ESD characterization and testing. This is shown in examples of (vf-)tlp, HMM and CDM results on test structures and products. Wear out effects lead to lower failure levels and should be minimized to obtain the correct pass/fail levels. 8A.2 Low Impedance Contact CDM Nathan Jack, Timothy J. Maloney, Intel Corporation Relay-based contact CDM (CCDM) is shown to closely replicate the waveforms and failure currents of legacy field-induced CDM when the system impedances are approximately matched. The reproducibility of the waveforms will be crucially important as CDM test levels decrease below 250V. Recommendations for inclusion in future standards are presented. 8A.3 Practical HBM Testing with Statistical Pin Combinations Wolfgang Stadler, Josef Niemesheim, Huelya Guerses, Oliver Hilbricht, Intel Mobile Communications; Andrea Boroni, Giuseppe Ballarin, STMicroelectronics; Evan Grund, Grund Technical Solutions Instead of using a pin group approach as defined in the current HBM standard JS-001, stressing statistically determined pin pairs can drastically reduce the stress count and the stress time. The correlation of different HBM test methods is discussed with different examples, proving the wide applicability of this approach. 8A.4 A Low-Impedance TLP Measurement System for Power Semiconductor Characterization up to 700V and 400A in the Microsecond Range Gabriel Cretu, Marius Cenusa, Martin Pfost, Reutlingen University; Kevni Bu yu ktas, Uwe Wahl, Infineon Technologies A TLP system with very low characteristic impedance of 1.5 Ω and selectable pulse length from 0.5 to 6 μs is presented. It covers the entire operation region of many power semiconductors up to 700 V and 400 A. Its applicability is demonstrated by determining the output characteristics for two CoolMOS devices up to destruction. Session 9A 10:50 AM-12:05 PM 9A: ESD Testing and Failure Analysis Moderator: Peter de Jong, Synopsys Inc. 9A.1 Using Long-Duration TLP to Debug & Even Predict an EOS Issue Dave Clarke, Stephen Heffernan, Analog Devices, Inc. This case study shows how long-duration TLP can be used to debug, replicate and even predict EOS issues. Once the EOS waveform characteristics are determined, it allows easier identification of the root cause of the EOS and therefore prevention of future occurrences. 9A.2 EOS Characterization Methodology Applied to a Disable Feature of ESD Power Clamps Jorge Loayza, Nicolas Guitard, Blaise Jacquier, Alexandre Dray, Divya Agarwal, Vicky Batra, STMicroelectronics; Bruno Allard, Luong Vie t Phung, Laboratoire Ampe re This work presents an EOS characterization methodology for ESD clamps. BigFET- based, SCR-based power clamps with and without disable feature are characterized. Robustness comparison is provided for the different ESD clamps, giving insights on improving IC robustness against undesired triggering during EOS events. 9A.3 Source of Miscorrelation of Product Level HBM to TLP Test Results Manjunatha Prabhu, Jian-Hsing Lee, Mahadeva Iyer Natarajan, Vasantha Kumar, Tsung-Che Tsai, Li Zhiqing, GLOBALFOUNDRIES Correlation between TLP and HBM test results at product level and/or complex ESD circuit is not feasible. In product level HBM testing there can be stress condition, which is worse at low current compared to high ESD current. Such results cannot be replicated in TLP. 29

30 30Workshops Workshops Chair: James Miller, Freescale Semiconductor, Inc. You are invited to send your comments/questions in advance to the respective workshop moderators via or at the ESDA web page ( TUESDAY SEPTEMBER 29 TH Session A: 5:30 p.m. - 7:00 p.m. (Parallel Sessions) A1. Strategies to Address Latch-up Test Program Complexity in Advanced Mixed Signal ICs Moderators: Marty Johnson, Texas Instruments Scott Ruth, Freescale Semiconductor, Inc. IC components are becoming increasingly complex, integrating any number of analog and digital interfaces as well as various topologies of on-chip voltage regulators. Furthermore, even the general purpose I/O (GPIO) is not what it used to be since it now may multiplex numerous types of analog and digital data through a single pin. With such complexity, is it possible to know a priori what is the worst-case operating mode - from a latch-up test perspective? If so, who is best positioned to make this judgment? If not, does it make sense to exercise all modes of operation? Is this practical? Does an ATE tester platform help with this aspect? How are people dealing with this complexity in practice? How often do we take into account the details of the system and a customer use case to reduce the complexity? Is it appropriate to take the path of least resistance or should we try our best to maximize test coverage? While we do not expect any easy answers to these difficult questions in this Workshop, we do anticipate a vigorous discussion. Please attend and offer your ideas. A2. Best Practices for ESD Robust SoC Integration of Commercial IP Moderators: Fabrice Blanc, ARM Peter de Jong, Synopsys Inc. CDM ESD failures internal to the core region have become prevalent for advanced technology ICs. A particular category of ESD issues is induced by the integration process of 3rd party IP into the SoC. It is the joint responsibility of both IP vendor and customer to minimize the ESD risks related to IP integration. This Workshop will address questions such as: What ESD measures should be included in the IP? How can the IP vendor maximize the probability of successful IP integration? What ESD related data and integration guidelines should be provided by the vendor? What efforts can reasonably be requested from the customer? Should industry best practices be documented and shared with IP vendors? There are a wide variety of IP categories, e.g. pure core or interface, including or excluding I/Os, fixed or variable I/O placement, etc. We will consider the questions in perspective of these different IP types. Your experience (good or bad) with 3rd party IP would be much appreciated in the discussion. A3. Implications of the New ANSI/ESD S2020 Specification Moderators: John Kinnear, IBM Corporation David Swenson, Affinity Static Control Consulting Scott Ward, Texas Instruments The S20.20 ESD control program is more than just a single document. It is a complete suite of documents that covers material compliance, training, periodic checks and proper safe handling procedures. A number of significant changes have been made to the S20.20 ESD control program. These changes were driven by new technologies and improved instrumentation. New technologies have driven the ESD targets to lower levels, thus improved ESD control programs are required to prevent ESD problems. In order to keep your factory in compliance, it is imperative to understand the modifications to the S20.20 specification and the phase-in plan for the 2014 S20.20 program.

31 WEDNESDAY SEPTEMBER 30 TH Session B: 5:30 p.m. - 7:00 p.m. (Parallel Sessions) B1. What Should Foundries Include in Their PDKs to Better Support Custom ESD Design? Moderators: Stephen Fairbanks, SRF Technologies David Klein, Synaptics Have you ever tried to fix a car blind-folded? As ESD engineers, we often face a similar challenge when designing custom on-chip ESD protection in foundry process technologies. Meeting the goal of first-time-right IP can be very difficult when the foundry does not provide adequate ESD-specific collateral. We find ourselves working blind, making educated guesses without sufficient information or models. What device data should be in these ESD kits? Are ESD-specific compact models expected? What DRC/ LVS/ERC verification infrastructure is needed to insure robust ESD design? Do foundries have an obligation to share this data? This Workshop is your chance to voice your opinion and list what ESD collateral is missing in standard foundry deliverables. B2. Is HBM-1000V/CDM-250V Now the Industry Default Qualification Target for IC Components? Moderators: Brett Carn, Intel Rita Horner, Synopsys Inc. It has been eight years since the ESD Industry Council first released White Paper 1, setting a 1kV HBM qualification target, and six years since White Paper 2 set a 250V CDM target. Yet, many IC suppliers, even companies whose logo is on the white paper s front page, have not yet moved to the Industry Council s recommendations. Cited reasons are numerous: competitive disadvantage if another supplier qualifies at higher levels, and OEM s belief that low-cost assembly houses don t control their manufacturing environment well enough. This workshop will explore qualification targets in practice right now and the reasons for them. Are there still misconceptions? Have new markets such as IoT and automotive changed the landscape? Did the Industry Council neglect key aspects in their findings? Should something further be done to make unified reduced qualification targets pervasive across the industry? B3. Component System Level ESD Design; Efforts by Auto Tier 1 s to Define Standard Tests Moderators: Reinhold Gaertner, Infineon Edgar Kuhn, Continental The Auto industry, particularly in Germany, is moving forward in an attempt to standardize test scenarios as an early measure of potential component system level robustness. This effort is driven, in part, by problems with waiting to perform indirect ESD tests on the final board application. With this approach, weaknesses may appear too late to improve the ESD performance, even with board layout changes. At this stage, if the weakness is in the MCU/ASIC IC, it is very difficult to correct the design. For this reason new ESD test methodologies are being developed to investigate ESD/ immunity performance in early ECU RFQ design phases. Ideally the new ESD procedures on MCU/ASIC ICs should consider both the final application environment in term of mechanics/layout, and the final OEM ESD requirements (RC network, ESD type Air/ Contact, etc.). Should these tests be standardized? Should they be applied in the semiconductor supplier or Tier1 s area? What kind of board should be used; a dedicated ESD board or TEM board? Are we seeking ESD radiated effects (E/H fields) or just the simple ESD conducted pulse? Please consider joining this Workshop and offering your ideas in this critical developing test area. 31

32 Exhibits You will find a broad spectrum of products and services for static protection, control, testing and analysis, as well as prominent trade publications all in one location for your convenience. Exhibits are open to the public. 32 Exhibitor Booth Number ACL Staticide, Inc. 302 Aidacom Technology (Shenzhen) Co., Ltd. 604 Ansys, Inc. 606 Barth Electronics, Inc. 200 Botron Company, Inc. 104 Carmel Oletius Ltd., Bazan Group 101 Conductive Containers, Inc. (CCI) 301 Core Insight, Inc. 612 Dangelmayer Associates 210 Desco Industries, Inc. 404 Dou Yee Enterprises (S) Pte Ltd. 706,708 Electro-Tech Systems, Inc. (ETS) 515 ESDEMC Technology, LLC 209 ESTION Technologies GmbH 512 Euclid Vidaro Mfg., Co. 516 GIBO/KODAMA Chairs 509 Grund Technical Solutions, Inc. 616 Hamamatsu Corporation 105 Hanwa Electronic Ind. Co., Ltd. 602 HPPI, GmbH 609 IEEE EMC Society 115 In Compliance 211 LINTEC of AMERICA Inc. 605 Lubrizol 505 Magwel 506 Megalin Source International Co., Ltd. 112 Mentor Graphics Corp. 510 Monroe Electronics Inc. 402 Moxtek, Inc. 700 NRD-Advanced Static Control, LLC 205 Polyonics 110 Prostat Corporation 410 RTP Company 500 Shanghai Chenlong Static Technology Co., Ltd. 610 Shenzhen Btree Industrial Co. Ltd. 511 Shishido Electrostatics, Ltd. - Static Clean 709 Sika Industrial Flooring 711 Silicon Frontline Technology Inc. 504 Simco-Ion Technology Group 309 Statico 503 Static Solutions, Inc. 216 Static Stop 212 Stephen Halperin & Associates Inc. 410 TDI International, Inc. 215 Tech Wear, Inc. 303 Tek Stil Concepts, Inc. 217 Thermo Fisher Scientific 315 Transforming Technologies 204 Trek, Inc. 611 Zhejiang Sanwei Anti-Electrostatic Equipment Co., Ltd. 705 Zhejiang Xianju Guoda Plastic Electronics Factory minute showcase presentations from exhibitors are scheduled at the beginning of select technical sessions. A complimentary coffee bar is available in the exhibit hall for all who visit. Lunch service will be available in the exhibit hall on Tuesday and Wednesday for anyone wishing to purchase lunch while visiting the exhibits. Exhibit Hours Monday, September 28 th 5:00 p.m. - 9:00 p.m. Tuesday, September 29 th 9:30 a.m. - 5:30 p.m. Wednesday, September 30 th 8:30 a.m. - 1:30 p.m.

33 EOS/ESD Association, Inc. EOS/ESD Association, Inc. Officers President Terry Welsher, Dangelmayer Associates LLC, Suwanee, GA Senior Vice President Gianluca Boselli, Texas Instruments, Inc., Dallas, TX Vice President Ginger Hansel, Dangelmayer Associates LLC, Austin, TX Treasurer John Kinnear Jr., IBM Corporation, Poughkeepsie, NY Secretary Alan Righter, Analog Devices, Inc., Wilmington, MA Past President Leo G. Henry, ESD/TLP Consultants LLC, Fremont, CA Headquarters Operations Lisa M. Pimpinella, Director of Operations Terry Finn, Marketing and Communications Program Manager Christina Earl, Standards Program Manager Board of Directors Gianluca Boselli, Texas Instruments, Inc., Dallas, TX Brett Carn, Intel, Hillsboro, OR Cheryl Checketts, Scottsdale, AZ Jeffrey Dunnihoo, Pragma Design, Bertram, TX Charvaka Duvvury, ESD Consulting LLC, Plano TX Reinhold Gaertner, Infineon Technologies, Neubiberg, GERMANY Harald Gossner, Intel Mobile Communications, Neubiberg, GERMANY Ginger Hansel, Dangelmayer Associates LLC, Austin, TX Leo G. Henry, ESD/TLP Consultants LLC, Fremont, CA Michael Khazhinsky, Silicon Laboratories, Inc., Austin, TX John Kinnear Jr., IBM Corporation, Poughkeepsie, NY Nathaniel Peachey, Qorvo, Greensboro, NC Lisa Pimpinella, EOS/ESD Association, Inc., Rome, NY Alan Righter, Analog Devices, Inc., Wilmington, MA Wolfgang Stadler, Intel Mobile Communications, Neubiberg, GERMANY David Swenson, Affinity Static Control LLC, Austin, TX Scott Ward, Texas Instruments, Inc., Dallas, TX Terry Welsher, Dangelmayer Associates LLC, Suwanee, GA Symposium Committees Steering Committee Technical Program Committee Symposium Business Unit Manager Chair: Junjun Li, Apple Gianluca Boselli, Texas Instruments, Inc., Dallas, TX General Chair Dolphin Abessolo-Bidzo, NXP Semiconductors Warren Anderson, Synopsys, Inc., Boxborough, MA Robert Ashton, On Semiconductor Vice General Chair Stephen Beebe, GLOBALFOUNDRIES, Inc. Melanie Etherton, Freescale Semiconductor, Inc., Austin, TX Fabrice Blanc, ARM Fabrice Caignet, LAAS/CNRS Tutorial Program Chair Yiqun Cao, Infineon Technologies Ginger Hansel, Dangelmayer Associates LLC, Austin, TX Victor Cao, GLOBALFOUNDRIES, Inc. Technical Program Chair Mike Chaine, Micron Technology, Inc. Junjun Li, Apple, Cupertino, CA Thomas Chang, IBM Corporation Workshops Chair Charles Chu, Maxim Integrated James Miller, Freescale Semiconductor, Inc., Austin, TX Paolo Colombo, STMicroelectronics Arrangements Chair Peter de Jong, Synopsys, Inc. Cheryl Checketts, Scottsdale, AZ Jeffrey Dunnihoo, Pragma Design Charvaka Duvvury, ESD Consulting LLC Registration Chair Farzan Farbiz, Texas Instruments, Inc. Raivo Leeto, Sandia National Laboratories, Albuquerque, NM Reinhold Gärtner, Infineon Technologies Robert Gauthier, IBM Corporation Audio/Visual Co-Chair Eleonora Gevinti, STMicroelectronics Lorenzo Cerati, STMicroelectronics, Agrate Brianza, ITALY Harald Gossner, Intel Mobile Communications Audio/Visual Co-Chair Evan Grund, Grund Technical Solutions, Inc. Guido Notermans, NXP Semiconductors, Hamburg, GERMANY Geert Heeling, imec Tutorial Audio/Visual Chair Mattew Hogan, Mentor Graphics Souvick Mitra, IBM Corporation, Essex Junction, VT Nathan Jack, Intel Corporation Michael Khazhinsky, Silicon Laboratories, Inc. Information Ming Dou Ker, NCTU David Swenson, Affinity Static Control LLC, Austin, TX John Kinnear, IBM Corporation Past General Chair Vladimir Kraz, OnFilter Harald Gossner, Intel Mobile Communications, Neubiberg, GERMANY Hans Kunz, Texas Instruments, Inc. ESDA Vice President Gianluca Boselli, Texas Instruments, Inc., Dallas, TX Publications & Marketing HQ Operations, EOS/ESD Association, Inc., Rome, NY Jean-Phillippe Laine, Freescale Semiconductor, Inc. Kitae Lee, Samsung Jam-Wen Lee, TSMC You Li, IBM Corporation Markus Mergens, QPX Rahul Mishra, IBM Corporation Souvick Mitra, IBM Corporation Guido Notermans, NXP Semiconductors Anirudh Oberoi, Silicon Labs Mototsugu Okushima, Renasas Nate Peachey, Qorvo David Pommerenke, Missouri University of Science and Technology Elyse Rosenbaum, University of Illinois at Urbana-Champaign Christian Russ, Intel Mobile Communications Scott Ruth, Freescale Semiconductor, Inc. Javier A. Salcedo, Analog Devices, Inc. Akram Salman, Texas Instruments, Inc. Mayank Shrivastava, Indian Institute of Science (IISc) Bangalore Jeremy Smallwood, Electrostatic Solutions, Ltd. Theo Smedes, NXP Semiconductors Ankit Srivastava, Qualcomm, Inc. Wolfgang Stadler, Intel Mobile Communications Michael Stockinger, Freescale Semiconductor, Inc. David Swenson, Affinity Static Control LLC Pasi Tamminen, Microsoft Augusto Tazzoli, Maxim Nitesh Trivedi, Infineon Technologies Vladislav Vashchenko, Maxim Integrated Heinrich Wolf, Fraunhofer EMFT Gene Worley, Qualcomm, Inc. Joshua Yoo, Core Insight, Inc. 33

34 Accomodations Peppermill Resort Hotel 2707 South Virginia Street, Reno, NV All reservations must be received by September 10, 2015 Room Rates Single/Double: $125 per night* Phone Reservation (reference group code AELEC15 ) Book reservations by 9/10/2015 (Please book early as a limited number of hotel rooms are available) Reservations Link: Resort fee included in the rate Credit card is required to make reservations, credit card information accepted via phone or fax only (not ). Name: Company: Address: City: State/Province: Zip/Postal Code: Country: Phone: Accommodations Requested ($125 Single/Double) King Double Number of People Accommodations under the Americans with Disabilities Act Room rates shown do not include applicable taxes and surcharges. Arrival Date: Departure Date: List all persons who will be sharing accommodations ROOM SCAMS-PIRATES/POACHING NOTICE: There are companies obtaining registration lists from public sources-do not respond to these solicitations concerning room reservations. In order to secure a room at the Peppermill Resort Hotel you must book through the proper official channel as provide above. Housing block pirates now routinely poach event attendees and exhibitors! The pirating companies gather group s contact information from published or online directories. They call attendees leaving the impression that they are official housing. They will also frequently cite an imminent sell-out of the block while urging you to secure housing immediately. Another tactic is to offer a room rate that is significantly less than the official rate. Please do not respond to these solicitations. Reservations: When reserving your room, in all instances, identify yourself as a participant of the EOS/ESD Symposium. Cancellation of reservation must be made at least seven days prior to arrival date or you will be charged one nights room/tax. Check-in Time is 4:00 p.m. Check-out Time is 12:00 Noon. Resort Fee: Resort fee includes internet access for hotel guests staying in the hotel in all public areas, sleeping rooms, and the Internet Cafe with increased internet download speed from 1.5 mbps to 7.0 mbps, complimentary business center access, incoming and outgoing faxes up to 5 pages, in-room coffee makers, use of the health club, pool, valet, access to the parking garage and surface parking, concierge, local and #800 phone calls, and shuttle service to and from the airport. Complimentary internet access in meeting rooms (only if you stay at The Peppermill). 34