Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs

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1 Power nd Slew-wre Clok Network Design for Through-Silion-Vi (TSV) sed 3D ICs Xin Zho nd Sung Kyu Lim Shool of Eletril nd Computer Engineering Georgi Institute of Tehnology, Atlnt, GA 3033, U.S.A. {xinzho, Astrt In this pper, three effetive design tehniques re presented to effetively redue the lok power onsumption nd slew of the 3D lok distriution network: (1) ontrolling the ound of through-silion-vis (TSVs) used in etween djent dies, () ontrolling the mximum lod pitne of the lok uffer, (3) djusting the lok soure lotion in the 3D stk. We disuss how these design ftors ffet the overll wirelength, lok power, slew, skew, nd routing ongestion in the prtil 3D lok network design. SPICE simultion indites tht: (1) 3D lok tree with multiple TSVs hieves up to 31% power sving, 5% wirelength sving nd etter slew ontrol s ompred with the single-tsv se; () y pling the lok soure on the middle die in the 3D stk, n dditionl 7.7% power svings, 9.% wirelength svings, nd 33% TSV svings re otined ompred with the lok soure on the topmost die. This work ims t helping designers onstrut relile low-power nd low-slew 3D lok network y mking the right deisions on TSV usge, lok uffer insertion, nd lok soure plement. I. INTRODUCTION In three-dimensionl integrted iruits (3D ICs), the lok distriution network spreds over the entire stk to distriute the lok signl to ll the sequentil elements. Clok skew, defined s the mximum differene in the lok signl rrivl time from the lok soure to ll the sinks, is required to e less thn 3%-4% of the lok period in n ggressive lok network design ording to ITRS projetion. Thus, lok skew ontrol, whih ws well studied in D ICs [1], is still primry ojetive in the 3D lok network design. Menwhile, the lok signl is distriuted not only long the X nd Y diretions, ut lso long the Z diretion using through-silion-vis (TSVs). The lok distriution network drives lrge pitive lods nd swithes t high swithing frequeny. This leds to n inresingly lrge proportion of the totl power of system dissipted in the lok distriution network. In some pplitions, the lok network itself is responsile for 5% [] nd even up to 50% [3] of the hip totl power onsumption. Thus, low power nd low slew rte still remin the importnt design gols in 3D lok network. 3D integrtion with TSVs hs een intensively studied in oth hip-to-hip nd hip-to-wfer ommunitions [4]. The frition nd hrteriztion of TSVs re eing explored in mny ompnies nd institutes [5]. TSV reliility issues re lso studied [6]. TSV provides the vertil interonnetion to deliver the lok signl to ll dies in the 3D stk. The TSV This mteril is sed upon the work supported y the Ntionl Siene Foundtion under CAREER Grnt No. CCF , the Center for Ciruit nd System Solutions (CS), nd the Interonnet Fous Center (IFC). usge is n importnt ftor tht hrterizes the eletril property of the lok network. In generl, the totl wirelength of the 3D lok network dereses signifintly if more TSVs re used [7], [8]. However, too mny TSVs often use routing ongestion nd yield redution. Therefore, it is importnt tht the power vs ongestion trdeoff is onsidered refully during the 3D lok network design. Minz et l. [7] studied the therml issue of the 3D lok network nd developed 3D lok routing lgorithm. However, this work does not onsider power onsumption or slew rte nd does not provide ny SPICE simultion results. Zho et l. [8] developed lok design method for pre-ond testing on 3D ICs. They lso disussed the impt of TSVs on the preond testle lok tree. In [9], Pvlidis et l. presented mesurement dt on frited 3D lok distriution network. In [10], Arunhlm nd Burleson used seprte lyer for the lok distriution network to redue power. Their simultions show 15%-0% power redution over the sme D hip lok network. However, these works use simple H-tree nd do not perform ny design-level optimiztion. In this pper, we nlyze the impt of TSV usge upper ound, lok soure lotion, nd mximum loding pitne of lok uffers on the wirelength, lok power, slew, skew, nd TSV ount of the 3D lok network. The ontriutions of this pper re s follows: We nlyze the impt of TSV usge on the wirelength nd lok power metris. Compred with the single-tsv lok network, the multi-tsv lok network hieves up to 31% power svings nd 5% wirelength svings. We nlyze the impt of lok soure lotion on the wirelength nd lok power metris. By pling the lok soure on the middle die, we otin dditionl 7.7% power svings, 9.% wirelength svings, nd 33% TSV ount svings ompred with the lok soure on the topmost die. We disuss the impt of TSV usge nd mximum lod pitne of lok uffers on lok slew ontrol. The multi-tsv usge helps to nrrow the slew distriution nd redue the mximum nd verge slew s ompred with the single-tsv se. In ddition, upper ound on the lok uffer lod pitne remins n effiient wy to ontrol the mximum slew for 3D lok network design. We vlidte our lims with SPICE simultion results on set of lrge enhmrk designs. Our power onsumption, skew, /10/$ IEEE 175

2 die3 die sr wire C w R w C w RTSV C TSV C TSV () TSV=1 TSV= TSV=4 die1 () uffer () TSV Fig. 1. Smple lok tree nd its eletril model. () smple 3-die lok network, where the lok soure is on die-3. Sink on die-1 uses -stk TSV, nd sink on die- uses 1-stk TSV to onnet to lok soure. () eletril models for lok wire segment, TSV, nd uffer/drivers. () e g d d d f e f e f h g h g h () nd slew metris re sed on SPICE simultion. II. MODELING AND SYNTHESIS OF 3D CLOCK TREE A. Eletril Model of 3D Clok Network In this pper, the 3D lok network is modeled s distriuted RC network. Figure 1 shows n illustrtion of 3-die lok interonnet, where the lok soure is loted on die-3, sink on die-1 onnets to the soure using -stk TSV, nd sink on die- onnets to the soure y 1-stk TSV. The sink nodes nd re modeled s pitive lods. Wire segments nd TSVs re modeled y π model. Eh uffer or driver is onstruted with two inverters. When vertil onnetion etween non-djent dies is required, e.g., die-1 nd die-3, we use stked TSV, where the TSV tht onnets die-1 nd die-, nd die- nd die-3 re vertilly ligned s shown in Figure 1(). This tll TSV is lled -stk TSV. A 6-die 3D stk utilizes, 1-stk, -stk,..., up to 5-stk TSV. B. 3D Clok Tree Synthesis Given set of lok sinks distriuted on multiple dies nd the TSV upper ound, 3D lok tree synthesis is to onstrut single 3D tree tht onnets ll the sinks on different dies under the TSV udget nd to minimize the lok skew nd power onsumption. Clok slew, defined s the trnsition time from 10% to 90% of lok signl t eh sink, is n dditionl design onstrint. In this pper, we set the lok slew to given vlue, usully is some perentge of the lok period. The TSV upper ound is defined s the mximum numer of TSVs llowed etween eh pir of djent dies in the 3D stk. TSV ound is usully deided efore lok synthesis nd is sed upon the proess tehnology. Different from TSV ound, #TSVs is the totl numer of TSVs generted y 3D lok tree synthesis. For n n-die 3D stk, #TSVs is usully less thn or equl to (n 1) TSV ound. The sis of our 3D lok tree synthesis lgorithm is [7], where we extend [7] so tht (1) we n hndle more thn dies, () we n deide on whih die of the 3D stk to ple the lok soure, (3) we perform uffer insertion to minimize lok slew. Our lgorithm onsists of two min steps: (1) 3D strt tree topology genertion, nd () emedding nd slewwre uffering. First, we generte 3D strt tree sed on 3D Method of Mens nd Medins (3D-MMM) lgorithm. The d e g f h e g d f h e g f d h Fig.. 3D strt trees with 3D-MMM lgorithm under vrious TSV upper ound. () D version, where thik lines denote TSV onnetion, () 3D version, () inry strt trees, where the dots denote TSVs. 3D-MMM lgorithm silly determines whih pir of nodes to onnet together nd use TSVs if neessry while uilding inry tree in top-down fshion. For n n-die lok tree, the 3D strt tree is n-olored inry tree to identify the die index of lok soure, sinks nd internl nodes. The gol of TSV usge is to evenly distriute the TSVs ross the die re nd stisfy the given TSV ound. A TSV is used if we deide to onnet pir of nodes in different dies. Figure shows n illustrtion of -die stk with vrious TSV upper ound. A lrger TSV ound tends to move TSVs loser to the sink nodes nd use more vertil lok onnetions thn horizontl onnetions. One 3D strt tree is otined, we use the deferredmerge emedding (DME) lgorithm [11] to geometrilly emed (= route) the strt tree under the zero-skew gol sed on Elmore dely model. Different from the existing D design [1], [13], [14], whih foused on slew-wre uffer insertion fter lok routing, our slew-wre uffering is performed during the ottom-up emedding proedure. The gol of slew-wre uffering is to lote uffers while merging su-sets, so tht the lod pitnes of uffers re within the given ound (CMAX). The impt of CMAX on 3D lok slew is disussed in setion III-C. Note tht this 3D-MMM lgorithm works in suh wy tht there is lwys one die tht ontins single tree tht onnets ll sinks on the die, wheres the sinks on other dies re onneted with multiple trees (= forest). In this se, the lok soure is loted on the die tht ontins the single tree. Figure 3 shows smple lok trees on die-1 nd die-3 of 6-die 3D stk. The tringle denotes the lok soure on die-3. Eh die ontins up to 0 TSVs. Note tht die-3 hs single glol tree tht onnets ll the sinks, nd die-1 ontins multiple lol trees tht re onneted to the lok soure using TSVs. 176

3 soure die 1 die 3 Fig. 3. Smple lok trees on die-1 nd die-3 of 6-die 3D lok network, where the lok soure is loted on die-3. Blk dots denote TSVs. TSV ound is set to 0. Die-1 ontins mny lol trees, wheres die-3 ontins single glol tree. C. Theoretil Upper Bound on TSV Usge In this setion, we disuss theoretil upper ound on TSV usge in terms of the lotion of lok soure. Given M sinks evenly distriuted on N dies, eh die ontins M/N sinks. Assume tht the lok soure is loted on die-s. In generl, group of sinks on die-i re onneted to the lok soure die (= die-s) y shring one (i 1)-stk TSV. In the worst se, however, eh sink uses its own (i 1)-stk TSV to onnet to the lok soure on die-s. The mximum TSV usge in this se n e expressed s: ( s 1 ) M N N (s i)+ (i s) i=1 i=s+1 Note tht we ount (i 1)-stk TSV s i 1 TSVs, i.e., we ount individul TSVs in the stked TSVs seprtely. For the 6-die lok network, lok soure loted on the topmost die (= die-6) leds to the worst-se TSV ount s: (M/6) 6 i= (i 1) =.5M; when the lok soure is loted on the middle die (= die-3), the worst-se TSV ount is: (M/6) ( i=1 (3 i)+ 6 i=4 (i 3)) = 1.5M, whih leds to 40% TSV svings. In Setion III-D, further disussions on the prtil 6-die 3D lok network is provided. III. SIMULATION AND DISCUSSIONS A. Simultion Setting In our simultion, we first onstrut 3D lok network y using the 3D lok network synthesis method shown in Setion II-B under the given TSV ound nd CMAX. We then extrt the netlist of the entire 3D lok network for SPICE simultion. Clok power minly omes from swithing pitne of interonnet, sink nodes, TSVs nd lok uffers. Using SPICE simultion, we otin the power onsumption of the entire lok network nd the timing informtion suh s propgtion dely, lok skew, nd slew. The tehnil prmeters re sed on 45nm PTM [15]: unit-length wire resistne is 0.1Ω/um, nd unit-length wire pitne is 0.fF/um.Weuse10um 10um vi-lst TSVs with thinned die height of 0um. The prsitis re: R TSV is 0.035Ω nd C TSV is 15.48fF. Clok frequeny is set to 1GHz with the supply voltge of 1.V. Clok skew is Fig. 4. Impt of TSV ound on the totl wirelength nd power of the 6-die lok network with 3101 sinks. The TSV usge is represented s the perentge of the totl numer of sinks. The seline is when the TSV ound is 1. The infinity mens TSV ound is relxed. Fig. 5. Sptil distriution of propgtion dely (in ns) nd lok skew (in ps) of the lok soure die. The TSV usge is 90% of the sink ount. onstrined to 4% of the lok period. Clok slew onstrint is set to 10% of the lok period. The mximum lod pitne of eh lok uffer, denoted CMAX, is set to 300fF for slew ontrol unless otherwise speified. Our disussions fous on 6-die 3D stk, nd the lok soure is loted on the topmost die unless speified otherwise. The IBM enhmrk r 5 [16] is used, whih is the iggest one ville in the suite. r 5 hs 3101 sink nodes with input pitne vrying from 30fF to 80fF.Siner 5 is originlly designed for D ICs, we rndomly distriute the sinks into 6 dies. We sle the footprint re y 6 to reflet the re redution in 3D design. B. Impt of TSV Bound on Wirelength nd Power Figure 4 shows the wirelength nd power onsumption trend of the 6-die lok network sed on the TSV ound. The TSV usge is represented s the perentge of the totl numer of sinks. Lrger TSV upper ound ould led to more TSV usge. Note tht the tul numer of TSVs used in the lok network my not e the sme s the ound euse our lok tree lgorithm deides the optiml TSV ount for mximum 177

4 TABLE I COMPARISONS OF WIRELENGTH(UM), POWER(MW), TSV COUNT, BUFFER COUNT AND SKEW(PS) AMONG SINGLE-TSV, BOUNDED MULTI-TSV AND RELAXED MULTI-TSV CASES Single TSV Bounded multi-tsv Relxed multi-tsv kt #Sinks #TSVs #Bufs WL Power Skew #TSVs #Bufs WL Power Skew #TSVs #Bufs WL Power Skew r r r die r r Avg Rtio r r r die r r Avg Rtio () slew rnge CMAX () slew distriution (ps) Fig. 6. Slew distriution of 6-die 3D lok tree mong ll sinks. Slew onstrint is set to 10% of the lok period, CMAX is 300fF. () single- TSV lok tree, () multiple-tsv lok tree. Fig. 7. Slew vritions nd power omprisons etween single-tsv nd multi-tsv lok trees. CMAX vries from 175fF to 300fF. wirelength redution. For exmple, when the TSV ound is set to infinity, our lok tree uses 478 TSVs, whih is round 150% of the numer of sinks (= 3101). Our seline 3D lok tree ontins only one TSV in etween djent dies, whih is equivlent to TSV ound of 1. This seline is the most strightforwrd wy to uild 3D lok tree tht uses the minimum possile TSVs. We oserve tht the totl wirelength nd power onsumption derese when using more TSVs. The power sving mostly omes from wirelength redution, euse the lok wire pitne signifintly ffets the overll power onsumed y the lok tree. In generl, 3D interonnets sed on TSVs hve shorter wirelength ompred with D ounterprts. In se of the single-tsv 3D lok tree, this opportunity is severely limited. In overll, our multiple-tsv ses outperform the single-tsv se y up to 5% in wirelength nd 31% in power onsumption. This trend llows us to hoose the right TSV ound for given power udget. If the power sving of 0% is required, the TSV ound, whih is equl to or lrger thn the ound of 70% TSV usge, n e hosen sed on the point A in Figure 4. One interesting oservtion is tht, s the TSV ound inreses, the numer of lol trees in the nonsoure die inreses while their size dereses. This mens tht multiple TSV se enourges more lol lok distriution in 3D designs while reduing the overll wirelength nd power. Tle I presents more detiled results on the TSV ound impt. The IBM enh r 1 -r 5 reusedin4-diend6-die 3D stks. For eh 3D design, we ompre three TSV-usge ses: 1) Single TSV, where TSV ound is 1; ) Bounded multi-tsv, where TSV ound is set to 0% of #sinks; 3) Relxed multi-tsv, where TSV ound is set to e infinity. The verge rtio shows the reltionships mong the three TSV usges in terms of uffer ount, wirelength nd power. First, totl wirelength nd lok power redue s TSV ound inreses. Bounded multi-tsv ses produe 34% nd 40% wirelength svings in the 4-die nd 6-die stk, respetively. In ddition, power sving is % nd 4% for 4-die nd 6-die. Inresing the TSV ound further redues wirelength 178

5 die3 die sr sr die1 ) ) Fig. 8. () Clok soure is loted on the topmost die, where one -stk TSV nd one 1-stk TSV re used, () lok soure is loted on the middle die, where two 1-stk TSV re used. TSV height (stked) Fig. 10. Distriution of TSV heights used for the lok soure on top-die vs middle-die. We report the totl numer of eh TSV height used in the lok tree. oserve tht the lok skew mong the 6 dies vries within [17.8ps, 1ps]. The skew of the entire lok network is 1ps (round % of lok period). Note tht our 3D lok tree synthesis lgorithm uilds zero-skew tree under the Elmore dely model, whih in prtie shows disrepny etween SPICE simultion results. Fig. 9. Impt of lok soure lotion (topmost vs middle) nd TSV ound on wirelength nd power. Bseline is the lok tree with one 5-stk TSV, where the lok soure is on the topmost die. The used TSV ount in this se is rnging from 80% to 10% of the totl sink ount (= 3101). nd power. As result, infinity TSV ound se leds to the mximum wirelength svings nd power svings, whih re 44% nd 51% wirelength svings, nd 9% nd 3% power redutions s ompred with the single-tsv usge in 4-die nd 6-die stk. Note tht these svings ome t higher TSV usge, whih my ffet the overll yield. Thus, TSV ound must e deided refully sed on the given TSV proess tehnology. Seond, multi-tsv ses redue the numer of long lok pths, whih in turn requires fewer uffers for slew ontrol. Compred with the single-tsv uffer usge, the ounded multi-tsv uses 13% nd 1% fewer uffers in 4-die nd 6- die, respetively; the relxed multi-tsv se uses 4% fewer uffers in oth 4-die nd 6-die. The redued #Bufs ontriutes to the lok power svings. Menwhile, redued uffers do not hrm the slew ontrol. Using multiple TSVs, we hieve etter slew distriution thn the single-tsv se, whih is shown in setion III-C. Third, lok skew for eh 3D lok network is onstrined within 30ps. In most ses, lok skew is less thn 0ps. In se of the 6-die 3D stk of r 5, Figure 5 shows the sptil distriution of propgtion dely nd lok skew of the die ontining the lok soure. TSV usge is 90% of #sinks. We C. Impt of TSV Bound nd CMAX on Slew Distriution TSV upper ound lso ffets the lok slew distriution. Figure 6 shows the slew distriution of the 6-die 3D lok tree for r 5 mong ll sinks. Clok slew onstrint is set to 100ps, whih is 10% of the lok period. Figure 6() shows the slew distriution of the single-tsv lok tree, wheres the Figure 6() shows the slew distriution of the multi-tsv lok tree. In the single-tsv lok tree, slew vries within [11.4ps, 86.ps] with verge slew 53.9ps. The slew distriution of the multi- TSV se is in the rnge of [10.9ps, 79.6ps] with verge slew vlue 4.6ps. Compred with the single-tsv se, the multi- TSV usge redues the mximum slew nd verge slew y 6.6ps nd 11.3ps, nd shows nrrower slew distriution. The min reson for the improved slew distriution of the multiple- TSV 3D tree is the shorter wirelength, whih in turn redues the verge soure-to-sink dely. Lower dely long the lok pth mens less slew degrdtion seen t the sink nodes. Thus, we oserve tht multiple TSVs re effetive in improving the slew distriution. Figure 7 shows the impt of CMAX, the mximum lok uffer lod pitne, on slew vritions (min, verge, mx) nd power onsumption in the single-tsv nd multi- TSV lok trees. First, CMAX remins effiient to ontrol the mximum slew in 3D lok network design. Both the single-tsv nd multi-tsv hve the similr trends s CMAX vrying from 300fF to 175fF. Smller CMAX redues the mximum slew, ut inreses the lok power. Tht is euse eh uffer stge is llowed to drive less pitne using smller CMAX, whih in turn requires more uffers nd thus onsumes more power. Seond, given ertin CMAX, the multi-tsv lok tree lwys hs smller mximum slew, smller verge slew, nd nrrower slew rnge, s ompred with the single-tsv ses. Third, we note tht the multi- TSV ses lwys onsume lower power thn single-tsv ses. Therefore, we onlude tht the multi-tsv se hs 179

6 n dvntge in hieving oth low power nd etter slew. D. Impt of Clok Soure Lotion on Power nd Wirelength As disussed in the previous setion, more TSVs mens lower wirelength nd lok power. However, more TSV lso mens more routing ongestion. It is thus importnt to exploit the trdeoffs mong power, TSV ount nd ongestion while designing 3D lok trees. In prtiulr, we oserve tht the deision on whih die to ontin the lok soure ffets those metris in signifint wy. Figure 8 shows n illustrtion. When the lok soure is loted on the topmost die s in Figure 8(), the lok tree utilizes one -stk TSV nd one 1-stk TSV. However, if the lok soure is loted on the middle die s in Figure 8(), the lok tree utilizes two 1- stk TSVs. In ddition, the overll wirelength is shorter if the soure is loted on the middle die. The routing ongestion is lso less severe with shorter wirelength nd shorter TSV heights. It is shown [17] tht stked TSV frition requires dditionl steps to lign the TSVs, nd tht the omplexity inreses s more nd more TSVs re to e ligned nd stked vertilly. Therefore, the tree with the lok soure loted on the middle die (= Figure 8()) potentilly hs higher yield. Our lok tree synthesis lgorithm tkes the soure lotion s n input, so generting the orresponding 3D tree is strightforwrd. Figure 9 vlidtes our oservtions, where we show the wirelength nd power redution trend with the soure loted on the topmost vs middle die. Note tht disussions on topmost die nd middle die lso pply to the ottom-most die nd middle die. We oserve the following: The overll wirelength nd power redution trend is similr in oth the topmost-die nd middle-die lok soure ses. However, we oserve tht the middle-die se shows more wirelength nd power svings. When TSV usge is 90% of #sinks, the middle-die se (point D nd point C in Figure 9) shows dditionl 7.7% power svings nd 9.% wirelength svings s ompred with the orresponding topmost-die se. The overll power nd wirelength sving ompred with the seline (= the single-tsv se) is 33% nd 53%, respetively. Given power udget, we oserve tht the middle-die se requires fewer TSVs to otin nerly the sme mount of power svings. If 0% power redution is desired, the point A nd B in Figure 9 hve the sme power onsumption, ut point A uses 33% fewer TSVs thn point B. The middle-die se redues the TSV usge nd hieves the sme power sving s ompred with the topmost-die se. Figure 10 shows the distriution of stked TSV heights used for the lok soure on topmost die vs middle die. We report the totl numer of eh TSV height used in the lok trees. The overll trend is tht the verge height of TSV is lower in the middle-die se. For exmple, the middle-die se uses more of shorter TSVs (1-stk, -stk) thn the topmostdie se. Note tht the middle-die se does not require 4-stk nd 5-stk TSVs. In overll, the totl TSV height is 5% shorter in the middle-die se. This hs positive impt on TSV yield euse tller TSVs (4-stk nd 5-stk) require higher preision lignment nd frition proess. IV. CONCLUSIONS In this pper, we explored the design optimiztion tehniques for relile low-power, low-slew 3D lok network design. SPICE simultions on the 3D lok networks provided the lok power nd timing informtion. We studied the impt of the TSV usge, the lok soure lotion nd mximum lok uffer lod pitne on vrious metris of 3D lok distriution network, inluding wirelength, lok power, slew, skew, nd totl TSV ount. We oserved tht using more TSVs helps redue the wirelength nd power, nd shows etter ontrol on the lok slew vritions. We lso disussed tht using smller mximum loding pitne on lok uffers effiiently lowers lok slew. In ddition, we showed tht the lok soure lotion lso ffets the 3D lok network in signifint wy: pling the lok soure on the middle die, ompred with the topmost die, redues lok slew nd TSV usge under the sme power udgets. REFERENCES [1] P. J. Restle nd et l., A lok distriution network for miroproessors, in Solid-Stte Ciruits, IEEE Journl of, vol. 36, no. 5, 001, pp [] E. Friedmn, Clok distriution networks in synhronous digitl integrtediruits, vol. 89, no. 5, My 001, pp [3] Q. K. Zhu, High-speed Clok Network Design, 003. [4] J.U.Knikeroker, P.S.Andry, nd et l., Three-dimensionl Silion Integrtion, in IBM Journl of Reserh nd Development, vol. 5, no. 6, 008, pp [5] J. Vrdmn, 3-D Through-Silion Vis Beome Relity, 007, [6] S. L. Wright, P. S. Andry, E. Sprogis, B. Dng, nd R. J. Polstre, Reliility testing of through-silion vis for high-urrent 3D pplitions, in Eletroni Components nd Tehnology Conferene, 008. ECTC th, 008, pp [7] J. Minz, X. Zho, nd S. K. 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