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Transcription:

Tessent Diagnosis Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third- party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: www.mentor.com/trademarks. The registered trademark Linux is used pursuant to a sublicense from LMI, the exclusive licensee of Linus Torvalds, owner of the mark on a world-wide basis. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/eula. Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777 Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: www.mentor.com SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form Part Number: 073567

Module 1: Introduction... 11 Objectives... 12 with YieldInsight Flow Overview... 13 Diagnosis The Task; Overview... 14 Diagnosis The Task; Analogy... 15 Test and Diagnosis Overview... 16 Tool or Methodology?... 17 Diagnosis Failure Mechanism Examples... 18 Benefit Overview... 19 Diagnosing Scan Failures Overview... 20 Scan Test... 21 Scan Diagnosis... 23 Scan Diagnosis Flow... 24 Traditional Scan Diagnosis... 25 Layout-Aware Scan Diagnosis... 26 Basic Overview... 27 Basic Flow Summary... 28 Diagnosis Types... 29 Purpose and Test Conditions by Mode... 30 Diagnosis Methods... 31 Point Tool vs. Server... 32 Technology Overview... 33 When to Use... 35 Getting Help With Tessent Tools... 36 I

SupportNet... 39 Lab 1... 40 Module 2: Verify Diagnosis Inputs... 41 Objectives... 42 Generalized DFT Design Flow... 43 DFT Design Flow: Tessent Tools... 44 Failure Diagnosis: Tools and Processes... 45 Focus of this Module... 46 Archiving Test Patterns: ATPG... 47 Archiving the Data for Diagnosis: ATPG... 48 Archiving Consistent Data Multiple Test Modes... 49 How Many Flat Models to Archive... 50 Adding Archiving of Flat Model to Your ATPG Flow... 51 Archiving for Diagnosis: ATPG Command Guide... 52 Modes and the Flat Model... 54 Archiving Consistent Data Best Practices... 55 Diagnosis Input... 56 Data Consistency - Overview... 57 Consistency Checks for Test Patterns... 58 Consistency Check for Failure Files... 60 Data Consistency Checks - Patterns and Design... 61 Data Consistency Checks Fail Files... 62 Some Pattern Verification Issues... 63 Diagnosis Pattern Mismatch Options... 64 Pattern Masking... 65 II

Mask Types... 66 Masking File Syntax Example... 67 Report Measure Cycles Command... 69 Report_Measure_Cycles Example... 70 Startup Cache... 71 "Consistency" Command Summary... 72 Lab 2... 73 Module 3: Failure Files... 75 Objectives... 76 Tools and Processes... 77 Focus of this Module... 78 Diagnosis What Do You Need From ATE?... 79 Preparing Diagnosis Failure Files... 80 Failure File Key Concepts... 81 Failure File Formatting Keywords... 82 Keywords... 84 Examples... 85 Diagnosis Failure Files... 86 Tracking Information Section... 87 Cycle Based Failure File Format... 88 Pattern Based Failure File Format... 89 Converting Between Pattern-Based and Cycle-Based... 90 Multiple Test Suites... 91 Multiple Test Suites Example... 92 Supplying Multiple Test Patterns... 93 III

Data Logging Best Practices... 94 Procedural Review... 95 Session Command Order Example... 96 Lab 3... 97 Module 4: Diagnosis Modes and Output... 99 Objectives... 100 Running... 101 Results... 102 Header Section... 103 Diagnosis Report High-Level View... 104 Diagnosis Result Key Concepts... 105 Symptom Summary... 106 Symptom Summary Example... 107 Understanding Reported Suspects... 108 Evaluating Reported Suspects Example... 109 Diagnosis Modes... 110 Mode 1: Chain Diagnosis... 111 Chain Diagnosis Internal Process... 113 Step 1: Identify Faulty Chains and Fault Type... 114 Chain Fault Models Determined by Chain Patterns... 115 Chain Fault Types SLOW_TO...... 116 Chain Fault Types FAST_TO...... 117 Step 2: Locate Defective Scan Chain Cell... 118 Chain Fault Types Stuck Faults... 119 Mode 1: Diagnosis Report Example... 120 IV

Mode 2: Logic Diagnosis... 121 Mode 2: Suspect Types... 122 Mode 2: Diagnosis Report Example... 123 Running... 125 Session Command Order Process Overview... 126 Session Command Order Example... 127 Dofiles... 128 Writing Diagnosis Results to a File... 129 DFTVisualizer... 130 Viewing the Diagnosis Results in the Schematic... 131 Viewing Pattern Data in the Schematic... 133 Viewing a Suspect in the Schematic... 134 Encoding Output... 135 Diagnosis Options in Tessent Shell... 137 Lab 4... 138 Module 5: Layout-Aware Diagnosis... 139 Objectives... 140 Module Overview... 141 What Is Layout-Aware Diagnosis?... 142 Basic/Layout-Aware Diagnosis: Comparison... 143 Layout-Aware Enclosing Circle Comparison... 144 Some Useful Definitions... 145 Basic Diagnosis Report Section... 146 Looking at Layout Suspects... 147 Logic Suspect Classification - Review... 150 V

Layout-Aware Suspect Classifications... 151 Separating Interconnect and Cell-Internal Defects... 152 Layout-Aware Bridge Suspects... 153 Layout-Aware Open Suspect... 154 Suspect Net and Defect Bounding Box... 155 XMAP Table Suspect Reporting... 157 XMAP Table Defect Reporting... 158 XMAP Table MD5... 159 Basic vs. Layout-Aware Diagnosis Accuracy... 160 Example 1... 161 Example 2... 162 Creating a Layout Database (LDB)... 163 LDB Creation Process... 164 Layout Verification Rules... 165 Layout-Verification Mismatch Report... 166 Layout Verification Issues Debugging... 167 RCD Constant Creation for YieldInsight Users... 168 DFM Signature Analysis for YieldInsight Users... 169 Basic vs. Layout-Aware Diagnosis... 170 Layout-Aware Diagnosis Flow... 171 Viewing Layout Suspects in Tessent YieldInsight... 172 Viewing Layout Suspects in Calibre DESIGNrev... 173 Writing a Layout Marker File... 174 Layout-Aware Diagnosis Limitations... 175 Lab 5... 176 VI

Module 6: Volume Diagnosis... 177 Objectives... 178 Volume Diagnosis... 179 Diagnosis Server Key Concepts... 180 Automating Volume Diagnosis... 181 File Management... 182 Directory Example... 183 Commands... 184 Failure File Processing Order... 185 Operational Modes... 186 Customizing Server... 187 Improving Diagnosis Throughput... 188 Reducing Diagnosis Startup Time... 189 Startup Cache Creation and Update... 190 Startup Cache Usage... 191 Fail File Considerations... 192 Pre-Production Test Program Flow... 193 Production Test Program Flow... 194 Lab 6... 195 Module 7: Advanced Topics... 197 Objectives... 198 Iterative Diagnosis... 199 Iterative Diagnosis Flow... 200 Running Iterative Diagnosis... 201 Iterative Diagnosis Limitations... 202 VII

Identifying Failing Scan Cells... 203 Identifying Failing Scan Cells Techniques... 204 Identifying Failing Scan Cells Bypass Patterns... 205 Identifying Failing Scan Cells read_failures... 206 Identifying Failing Scan Cells 1hot... 207 Identifying Failing Scan Cells 1hot Patterns... 208 Identifying Failing Scan Cells 1hot Post ATE... 209 Identifying Failing Scan Cells Scan Cell Profiling... 210 Identifying Failing Scan Cells Profiling Score... 211 Identifying Failing Scan Cells Scan Cell Profiling Example... 212 Delay Fault Testing... 213 Diagnosing Frequency Dependent Failures... 214 Diagnosing Frequency Dependent Failures Another View... 215 Diagnosing Frequency Dependent Defects... 216 Running Gross-Delay Diagnosis... 217 Gross-Delay Diagnosis Report Snippet... 218 Diagnosing Slow Paths... 219 Reporting Paths for At-Speed Faults... 220 At-Speed Diagnosis Report File Snippet... 221 At-Speed Diagnosis Exploring the Suspect... 222 write_failing_paths Example Output... 223 IDDQ Diagnosis... 224 IDDQ Diagnosis File Examples... 225 Overriding Chain Diagnosis Aborts... 226 Bench-top ATPG Bring-up: Tessent SiliconInsight... 227 VIII

Tessent SiliconInsight Setup... 228 Lab 7... 229 IX