IFIP/IEEE VLSI-SoC 18 th International Conference

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1 IFIP/IEEE VLSI-SoC 18 th International Conference on Very Large Scale Integration VLSI-SoC 2010 (Madrid, Spain) September 27-29, 2010 Prof. David Atienza

2 The City: Madrid Easily accessible EU & America >30 flights daily EU Easyjet, Virgin, RyanAir, >20 flights daily from Americas Historical Puerta Alcala city Plaza Mayor Largest city in Spain: 602 KM 2 Population: 5.84M Romans & Muslims (9 th ) Cosmopolitan Buen Retiro 2006: Park 40% foreigners Royal Palace Complete transportation 10 metro lines, 150 buses Large academic tradition Atocha 12 Train universities Station (6 public, 7 priv.) Prado Museum Debod s Temple Twin Kio (bended) Towers

3 Location CS School/UCM Created in 1991 (new building in 2003) Students: ~3000 ; Teachers: ~200 (still growing) Facilities Auditorium with capacity for 150 attendees 3 Meeting rooms: capacity from 35 to 80 people Cafeteria and registration desk

4 Technical Programme (1/2).. Invited keynote speakers: Prof. Subhasish Mitra, Stanford U. Prof. Giovanni De Micheli, EPFL Dr. Sani Nassif, IBM Prof. Nick Dutt, UC Irvine Special industrial session Green computing and datacenters: IBM Zürich, Google, Yahoo, ST Bioengineering VLSI Hotels prices for you to come! single: /night (163 B$-250B$/night) double: /night (200 B$-300B$/night) Conference special theme: Green computing

5 Technical Programme (2/2) Day 1 Monday, September 27th Day 2 Tuesday, September 28th Day 3 Wednesday, September 29th 8:30 9:00 Registration and Opening 8:30 9:00 9:00 9:30 Keynote 1 (Auditorium) Keynote 2 (Auditorium) 9:00 9:30 9:30 10:00 Prof. Subhasish Mitra Stanford Univ. Prof. Giovanni De Micheli (EPFL) 9:30 10:00 10:00 10:30 Coffee break Coffee break Keynote 3 (Auditorium) 10:00 10:30 10:30 11:00 Session 1 Session 2 Session 5 Session 6 Dr. Sani Nassif IBM 10:30 11:00 11:00 11:30 Coffee break 11:00 11:30 11:30 12:00 Session 9 Session 10 11:30 12:00 12:00 12:30 12:00 12:30 12:30 13:00 Lunch Lunch 12:30 13:00 13:00 13:30 Lunch 13:00 13:30 13:30 14:0014:00 Keynote 2 (Auditorium) Session 7 Session 8 13:30 14:0014:00 14:00 14:30 Prof. Nikil Dutt UC. Irvine (Special Session 1) Session 11 Session 12 14:00 14:30 14:30 15:30 Poster Session 1 "Green Computing" ( Special Session 2) 14:00 15:30 15:30 16:00 and coffee break Coffee break Coffee break 15:30 16:00 16:00 18:00 Session 3 Session 4 PhD Forum Session 13 Session 14 16:00 18:00 18:00 20:00 Social event (tour in Madrid) 18:00 20: :00 1:00 Gala dinner with flamenco show 21:00 1:00

6 2 Social Events (visit to Madrid and 2 Social Events (visit to Madrid and dinner, flamenco and dancing test)

7 Final Call for Papers Website already open: - Easychair system (free), - DUDE replication of papers (CEDA) Paper/PhD Submissions: March 28, 2010 Special Session Proposal: March 28, 2010 Notification of acceptance: June 16, 2010 Camera-ready: July 11, 2010

8 Organizing Committee (1/2) General Chair David Atienza, EPFL, Switzerland Program Co-Chairs Andrea Acquaviva, Politecnico di Torino, Italy Jose L. Ayala, Complutense U. (UCM), Madrid, Spain Rajesh Gupta, UCSD, CA, USA Panels/Special Sessions Co-Chairs Ayse K. Coskun, Boston University, USA Luca Benini, Univ. of Bologna, Italy Publications Co-Chairs Chairs Ricardo Reis, UFRGS, Brazil Jose I. Hidalgo, Olcoz, UCM, Madrid, Spain Publicity Co-Chairs Chairs Praveen Raghavan, IMEC, Belgium PhD Forum Co-Chairs Matthew Guthaus, UCSC, USA Andreas Burg, ETHZ, Switzerland

9 Organizing Committee (2/2) Finance/Local arrangements Chair Katzalin Olcoz, UCM, Spain Fernando Rincon, Univ. Castilla La Mancha, Spain Steering Committee VLSI-SoC Manfred Glesner, TU Darmstadt, Germany Luis M. Silveira, INESC ID, Portugal Salvador Mir, TIMA, France Ricardo Reis, UFRGS, Brazil Michel Robert, U. Montpellier, France Institutional Relations Co-Chairs Francisco Tirado, UCM, Spain Román Hermida, UCM, Spain Invited Members of IFIP WG10.5 & IFIP/EEE VLSI SoC

10 Topics Technical Programme 12 Topics, 2 Co-Chairs per topic: Analog, Digital, and Mixed-Signal IC Design 3-D Integration and Physical Design Deep Submicron Design and Modeling Issues, New Devices and MEMS CAD and Tools, Testability and Design for Test Digital Signal Processing and Image Processing IC Design Prototyping, Validation, Verification, Modeling and Simulation System-on-Chip Design Embedded Systems Design and Real-Time Systems New Architectures and Compilers, Reconfigurable Systems Logic and High-Level Synthesis New Applications (bio-systems, sensor networks, automotive, security, communications, etc.) Low-Power Design

11 Income and Financial support Registration fees (break-even with 80 regs.) IEEE/IFIP students (7%/3%), 225 / 480 IEEE/IFIP Members (45%/5%), 400 / 600 NO IEEE/IFIP Students (27%/3%), 400 / 550 NO IEEE/IFIP Members (7%/3%), 550 / 700 TOTAL EXPECTED (100 people): ~50,000 Sponsoring IFIP, WG 10.5 (50%) IEEE Council on EDA (CEDA, 25%) IEEE Circuits and Systems Society (CASS, 25%) CS School and Complutense University Spanish Research Agency (~5000 )

12 VLSI-SoC 2010 ( See you next in October in Madrid!

ReCoSoC 2017 Close Report

ReCoSoC 2017 Close Report 1. Overview of the technical program: The technical program was organized as a single track, including 6 regular sessions, 2 special sessions and 5 keynote talks, spread over